40 bit DSP Adder
  • Supports 3 different 40-bit inputs
    • Zero (used for the DSP CLR and NEG)
    • ACCA or ACCB
    • Output of the Sign Extension Logic
  • One adder input may be complemented
    • Required by MPY.N, MSC, NEG and SUB
  • Adder generates output status signals
    • Overflow and Saturation bits in STATUS Register
    • Conditional branch instruction support

The 40-bit DSP Adder supports three different 40-bit inputs. The inputs may be 0, which is used for the DSP CLR and NEG instructions, may come from an Accumulator, (ACCA or ACCB), or be outputs of the Sign Extension logic. The selection of the inputs is based upon the instruction executed, and is transparent to the user, meaning that it is handled by the instruction decoding.

All Adder operations are signed, and one input to the Adder may also be negated. This feature provides support for the DSP instructions Multiply and Negate (MPY.N), Multiply and Subtract (MSC), Accumulator Negate (NEG) and Accumulator Subtract (SUB).

The Adder generates status bits which indicate overflow and saturation. The different saturation modes are user selectable, and are discussed later in this class. The architecture does provide conditional branch instruction support for these status bits, which facilitates efficient handling of overflow and saturation conditions in software. Lastly, note that MCU ADD instructions do not utilize the DSP Adder, they use the MCU ALU.

SR: CPU STATUS Register

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2 IPL1 IPL0 RA N OV Z C
bit 7 bit 0
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