Zero Overhead Loops
- Zero Overhead Loop
- A zero overhead loop is a loop whose endpoints are determined by hardware so that no software is required to determine when the loop has ended and must return to the beginning. Loops are the heart of DSP algorithms and it is because of their importance that DSP hardware supports them.
The most fundamental mathematical operation in DSP is shown in Equation 1: the sum of products (dot product). Zero overhead looping is required by the repetitive nature of the kernel equation. The multiply-accumulate function and the data fetches required are repeated N times every time the kernel function is calculated.
(1)\begin{align} y[n] = \sum_{k=0}^{N-1} h[k]*x[n-k] \end{align}
REPEAT Instruction
The REPEAT instruction causes the following instruction in code to be repeated n+1 times, where n may be a 14-bit literal or the 14 LSB of any W register.
REPEAT #lit14 or REPEAT Wn
- Range is 0 to 16383 instructions
- Effect is 1 to 16384 executions
- Loop count held in RCOUNT register
- STATUS<RA> bit set when RCOUNT > 1
- STATUS<RA> bit is cleared when RCOUNT = 1
- REPEAT instruction is interruptible
- RA bit is pushed on stack (SRL) on interrupt
- RCOUNT must be pushed onto stack before executing any REPEAT loops within an ISR
- Manually clearing RCOUNT exits the loop
- Can also exit by clearing STATUS<RA> bit
- REPEAT loop restrictions
- Any instruction can follow a REPEAT except:
- Program Flow instructions (CALL, BRA, etc)
- DO, REPEAT, DISI, LNK, ULNK, PWRSAV, RESET
- Any instruction can follow a REPEAT except:
SR: CPU STATUS Register
| R-0 | R-0 | R/C-0 | R/C-0 | R-0 | R/C-0 | R-0 | R/W-0 |
| OA | OB | SA | SB | OAB | SAB | DA | DC |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| IPL2 | IPL1 | IPL0 | RA | N | OV | Z | C |
| bit 7 | bit 0 |
REPEAT Instruction Examples
DO Instruction
The DO instruction repeats a set of instructions n+1 times, where n may be a 14-bit constant or the lower 14 bits of any W register.
- Loop start address stored in DOSTART
- Loop end address stored in DOEND
- Loop count held in DCOUNT register
- Loop size
- Minimum of 2 instructions
- Maximum of 32k instructions
- Restrictions
- Last two instructions in the loop cannot be:
- DO or REPEAT
- Instruction that changes program flow control
- Last two instructions in the loop cannot be:
- Interruptible, supports 7 levels of nesting
-
- One automatically via shadow registers
- Six by manually managing associated registers
-
- 7 levels of DO loops can exist in SW
- Six levels of nested DO loops allowed
- DO SFRs are shadowed automatically when a second DO instruction is executed (single level of nesting)
- Additional levels of nesting require user to stack the DO SFRs
- DO nesting level bits, CORCON:DL<2:0>, are automatically updated by hardware
- STATUS<DA> bit set when DL<2:0> does NOT equal 0 and DCOUNT > 1
SR: CPU STATUS Register
| R-0 | R-0 | R/C-0 | R/C-0 | R-0 | R/C-0 | R-0 | R/W-0 |
| OA | OB | SA | SB | OAB | SAB | DA | DC |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| IPL2 | IPL1 | IPL0 | RA | N | OV | Z | C |
| bit 7 | bit 0 |
CORCON: Core Control Register
| U-0 | U-0 | U-0 | R/W-0 | R/W-0 | R-0 | R-0 | R-0 |
| — | — | — | US | EDT | DL2 | DL1 | DL0 |
| bit 15 | bit 8 |
| R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/C-0 | R/W-0 | R/W-0 | R/W-0 |
| SATA | SATB | SATDW | ACCSAT | IPL3 | PSV | RND | IF |
| bit 7 | bit 0 |