CAN bus controller FIFO Error

Why does the FNRB bit value in the CiFIFO register not indicate the correct read buffer but indicates that the buffer has already been read?

This problem can arise if the receive and transmit channels have been assigned the same DMA channel.

This is applicable to all dsPIC33FJ and dsPIC33EP devices. This may also be applicable to PIC24HJ devices as they may be using the same CAN module as in the dsPIC33EP and FJ families.

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