KSZ8081 - Software Reset Timing Specification Details

For bit 15 of register 0h software reset, there is no specification. This bit is a self-clearing (SC) bit and sets all registers to their default value. The time is less than 1 µs from setting this bit to '1' and back to '0' from SC.

You can read/write all registers immediately after setting register 0h, bit 15. The bit 15 SC needs about four Management Data Clock (MDC) clock cycles, therefore it depends on the MDC clock frequency used.

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