(XC32) How to use L1 cache in PIC32MZ devices?

For PIC32 devices featuring an L1 data cache, data variables are by default allocated to the KSEG0 data-memory region (kseg0_data_mem). KSEG0 data-memory region is considered as cacheable and this makes the variables accessible through the L1 cache. So, the linker-allocated heap and stack are allocated to the KSEG0 region.

At Reset, code execution occurs from KSEG1 using uncached access. This is necessary as the cache cannot be used until it is initialized by start-up code. Once the cache is initialized, code execution can occur from KSEG0, which utilizes the cache for optimum performance. The default cache policy for the PIC32MZ is present in the start-up code supplied with the compiler.

Since the default stack is allocated to the cached KSEG0 region, run-time allocation of uncached memory must come from the heap. The compiler provides two functional equivalents to malloc() and free() to create uncached variables at run-time. These functions are ‘__pic32_alloc_coherent’ and ‘__pic32_free_coherent’. In a similar way, the coherent variable attribute will be allocated to the kseg1_data_mem region.

buffer will be allocated in KSEG1 region.


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