Step 2.1: Configure Audio CODEC (AK4953)
Expand the Harmony Framework Configuration > Drivers > CODEC selection tree.
Check the Use Codec AK 4953? Box
A default value for Volume is specified. You can change the value depending on your requirement.
Do not check Specify MCLK value. A default value of 256 for MCLK is selected under I2S driver configuration options MCLK Sampling rate Multiplier
Only one client of the CODEC driver needs to be opened, therefore retain the Number of AK4953 Driver Clients value to 1.
The AK4953 Driver supports only one instance of AK4953 CODEC module. AK4953 driver is a single instance driver. Therefore default instance of Codec AK4953 Driver Instance 0 is selected.
Select the I2S driver (used for data interface) instance as DRV_I2S_INDEX_0. The AK4953 driver uses I2S interface for the Audio data transfer to/from the PIC32 microcontroller. PIC32MZ2048EFH144 device supports multiple instances of I2S modules. An instance (Instance 0) for Audio data communication is selected.
Select the I2C driver (used for control interface) instance as DRV_I2C_INDEX_0 or 0. The AK4953 driver uses I2C interface for the Audio control transfers to/from the PIC32 microcontroller. The control transfers exchanges commands to/from the AK4953 CODEC to configure and/or read the initialized/existing configuration. PIC32MZ2048EFH144 device supports multiple instances of I2C modules. An instance (Instance 0) for Audio control communication is selected.
The CODEC devices need a fine clock source to generate accurate audio sampling rates. The clock source (MCLK from the CODEC device’s perspective) can be generated internally by the CODEC device.
PIC32 devices have a flexible reference clock output. The reference clock output module (REFCLKO) can be used to generate the fractional clock that can be used by audio CODEC/DACs to accommodate various sample rates.
The MCLK value represents the multiplier to the sampling frequency (LRCK) which produces the value for the master/reference clock (MCLK/REFCLOCK) to the CODEC. This value should be one of the fs values supported by the CODEC for various sampling rates.
For example: For 256 fs, The MCLK value of 256 for a sampling rate 48000 Hz would generate a MCLK/REFCLOCK of 12288000 Hz. By default, an MCLK value of 256 is selected. This is also shown in the default I2S driver configuration options MCLK Sampling rate Multiplier. If you intend to select a different MCLK value, check Specify MCLK value. It shows the following selectable options: 128, 192, 256, 384, 512, 768, and 1152.
Step 2.2: Configure I2C driver for CODEC
In AK4953 CODEC driver configurations, I2C is selected as the control interface medium (expand Harmony Framework Configuration > Drivers > CODEC > Use Codec AK4953? selection tree to see this). Next, configure the I2C interface driver.
Expand the Harmony Framework Configuration > Drivers > I2C selection tree.
The Use I2C Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I2C driver.
Select Dynamic for the Driver Implementation. A "Dynamic" I2C driver implementation will allow the implementation to be used for another instance of I2C module in this lab (needed for the touch screen).
Check the Interrupt mode option. This allows I2C data completion events to be detected asynchronously, without the need for polling for the transfer to complete. This is necessary because by the end of the lab, you will add a number of Harmony drivers, system services and middleware libraries. All these Harmony modules have to cooperatively run without blocking the processor.
Keep the Number of I2C Driver Clients and Number of I2C Driver Instances set to "1" since at this time I2C is only used to interface with the AK4953 CODEC. You will increase this number in a following lab to enable this driver to support multiple I2C interfaces.
Check Include Force Write I2C Function. This will include an API that sends data to the slave even if the slave NACKs data. This is needed by the AK4953 CODEC since it NACKs I2C data during the initialization sequence.
Under I2C Driver Instance 0, keep Use Bit Bang I2C Implementation? unchecked. Since the hardware I2C instance is used, use the driver for the real hardware instead of a bit banged driver implementation.
Select I2C_ID_2 as I2C Module ID. I2C module instance 2 is interfaced to the AK4953 CODEC’s control interface.
"I2C_ID_2" refers to the PIC32 I2C2 peripheral (using pins SCL2 & SDA2). These pins are connected to the AK4953 audio CODEC on the MEB II board.
Retain default value DRV_I2C_MODE_MASTER as Operation Mode. PIC32 I2C module 2 will act as master, and the AK4953 CODEC module control interface (I2C) will act as a slave.
Retain default value for Master Interrupt Priority and Master Interrupt Sub-priority as INT_PRIORITY_LEVEL1 and INT_SUBPRIORITY_LEVEL0 respectively. The CODEC I2C events needs to be signaled at higher priority.
Retain default value for Error Interrupt Priority and Error Interrupt Sub-priority as INT_PRIORITY_LEVEL1 and INT_SUBPRIORITY_LEVEL0 respectively.
Baud Rate generator clock is configured to 99 MHz; this is derived from the Peripheral bus 2 clock frequency generated from 198 MHz system clock.
Retain default value of 50 KHz for I2C CLOCK FREQUENCY. The AK4953 CODEC supports fast I2C control interface (up to 400 kHz).
Retain Slew Rate Control unchecked. This function enables the I2C module to use high frequency signalling, allowing it to use the 400 kHz and 1 MHz signalling rates.
Step 2.3: Verify/Set the I/O Pins Used by I2C Module
Step 2.4: Configure I2S driver for CODEC
In AK4953 CODEC driver configurations, "I2S" is selected as the Audio data interface medium. Next, configure the I2S interface driver.
Expand the Harmony Framework Configuration > Drivers > I2S selection tree.
The Use I2S Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I2S driver.
Expand the Use I2S Driver? Option.
"Dynamic" for Driver Implementation is selected by default and greyed out. The I2S driver does not support static implementation yet.
Check the box beside DMA Mode. Under DMA Mode, make sure the Transmit DMA Support and Enable DMA Channel Interrupts? boxes are checked. Transmit DMA Support is enabled to use DMA channels to transfer Audio Data from memory to I2S buffers. DMA Channel is interrupt enabled to allow DMA transfer completion notification.
Retain Stop in Idle Mode as it is.
Retain default Sampling Rate as 48000. This is the initial value of sampling rate.
Retain default value of 256 for MCLK Sampling rate Multiplier. The AK4953 CODEC supports 256fs with 48000 Hz sampling rate for generating the REFCLOCK.
Retain default value of 4 for Master Clock/Bit Clock ratio.
For sampling rate 48000 Hz and MCLK Sampling rate multiplier value of 256, The Mater Clock (MCLK) or Reference clock (REFCLOCK) = 256 * 48000 = 12,288,000 Hz. The common Bit Clock that can be generated for the given combination of MCLK and Sampling rate would be REFCLOCK/1, REFCLOCK/2, REFCLOCK/4 or REFCLOCK/8.
For Example: AK4953 CODEC supports bit clock (BCLK) value as either 32fs or 64fs. For 48000 Hz sampling rate, the Bit clock (BCLK) would be 64 * 48000 = 3072000 Hz. Therefore the MCLK/BCLK ratio is 12288000/3072000 = 4.
Retain default value of 1 set for Number of I2S Driver Clients and Number of I2S Driver Instances . The I2S interface is used only for Audio playback, therefore one instance of I2S driver and its client is sufficient.
Under I2S Driver Instance 0, Retain SPI_ID_1 as I2S Module ID. The PIC32's SPI/I2S1 peripheral (PIC32 pins: SCK1, SDI1, SDO1, /SS1) is interfaced to the AK4953 CODEC’s data lines.
Retain default value of Usage Mode as DRV_I2S_MODE_MASTER. It indicates whether the I2S instance will act as a Master or Slave. In Master mode PIC32 generates the BCLK to the Slave. In Slave mode PIC32 receives BCLK from the I2S Master. In the interface to AK4953 CODEC. PIC32 I2S will act as a Master and hence generates the BCLK (Bit Clock).
Retain default value of Baud Clock as SPI_BAUD_RATE_MCLK_CLOCK. Indicates that the system clock of 198MHz is used to generate the baud rate.
Retain default value of Clock Mode as
DRV_I2S_CLOCK_MODE_IDLE_HIGH_EDGE_FALL. The default polarity for I2S protocol.
Change Audio Communication Width to
SPI_AUDIO_COMMUNICATION_16DATA_16FIFO_32CHANNEL. In the scope of this lab CD quality Audio playback is supported, therefore setting 16 bit Audio data per channel, 32 bit channel width.
Retain default value of Audio Mode as SPI_AUDIO_TRANSMIT_STEREO. The lab supports stereo Audio Playback.
DRV_I2S_MODE_MASTER indicates whether the I2S instance will act as a Master or Slave. In Master mode PIC32 generates the BCLK to the Slave. In Slave mode PIC32 receives BCLK from the I2S Master. In the interface to AK4953 CODEC. PIC32 I2S will act as a Master and hence generates the BCLK (Bit Clock).
Retain default value of Input Sample Phase Selection as SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE. The default phase for I2S protocol.
Retain default value of Audio Protocol Mode as DRV_I2S_AUDIO_I2S. I2S protocol interface mode is chosen as it is supported by AK4953 CODEC.
Retain Queue Size Transmit to 3. This will allow queuing of up to 3 Audio buffer objects at a time.
Set Queue Size Receive to 1. Receive path is not utilized and hence a minimal value of 1 buffer object is set.
Retain Transmit DMA Channel Instance to 0. DMA Channel Instance 0 is used for Audio data transfer.
Step 2.5: Configure CODEC Input Clock
The PIC32 acts as I2S Master to the AK4953 CODEC. It needs to give the reference clock (REFCLOCK) or External Master Clock input (MCKI) to the CODEC in addition to the Bit clock (BCLK).
Expand the Harmony Framework Configuration > Options > System Services > Clock selection tree.
Expand Use Clock System Service?
Click Execute on Launch Clock Configurator
Locate the Reference Clock block. By default Reference Clock #1 tab is selected. The Reference Clock #1 enables configuring reference clock to SPI/I2S, PPS.
Check ON box. This enables the reference clock circuitry.
Click the Auto-Calculate button to generate the Reference Clock #1. It opens up a window Reference Clock Divisor and Trim Auto Calculator
Verify that the Reference Clock Divisor and Trim Auto Calculator show the desired Reference Clock and Sampling values to be generated. The values are generated from the MCLK multiplier and sampling rate specified in CODEC/I2S driver configuration.
Select the radio button Target I2S Input Frequency and click Apply button. The Target I2S Input Frequency is the reference clock input to the AK4953 CODEC.
If Target I2S Input Frequency is shown as 0, some I2S configuration is not done properly. Deselect and Re-configure the I2S driver as explained above and come back to this step.
Click on the OE button to enable the Reference Clock #1 output.
It is important to note that a reference clock of 12288000 Hz cannot be accurately generated from a system clock of 200 MHz. It is for this reason that the system clock is configured to 198 MHz, during the oscillator settings step.
Step 2.6: Configure the DMA System Service for Audio
The I2S driver has been configured to use a DMA channel for transferring Audio data to the CODEC.
Expand the Harmony Framework Configuration > Options > System Services > DMA selection tree.
Expand Use DMA System Service?
Retain Select Service Mode as Dynamic. This enables the same driver instance to manage multiple DMA channels (if required).
Keep the Number of DMA Channel Instances at 1. One DMA channel instance is used by I2S.
Expand the DMA Channel Instance 0. This is the instance set by the I2S driver for transferring audio data.
Under DMA Channel, Select DMA_CHANNEL_2. DMA Channel 2 will be used for I2S data transfer.
Step 2.7: Verify/Set the I/O Pins Used by I2S Module
Select the MPLAB Harmony Configurator tab and Pin Diagram sub-tab. In the lower window of MPLAB Harmony Configurator select the “Pin table” tab
Map REFCLOCK1 signal to pin RPD15. (For schematic, Refer Multimedia Expansion Board II (MEB II) User’s Guide)
Map I2S1 signals SDI1, SDO1 and SS1(out) signals to pins RPD14, RPB10 and RPF12. (For the schematic, refer to the Multimedia Expansion Board II (MEB II) User’s Guide)
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