Memory Organization

Enhanced Mid-Range PIC^® MCUs can contain up to 4096 bytes of addressable data memory. Data memory is partitioned in up to 32 memory banks with 128 bytes in each bank.

PIC16F1xxx data memory contains 5 data elements:

• Core Registers
• Special Function Registers
• General Purpose Memory
• Common Memory
• Shadow Registers

---

Core Registers

The first 12 entries of each PIC16F1xxx data memory bank contain registers referred to as the core registers. These 12 registers are repeated on each bank. The core registers can be accessed from any active bank.

Core Registers include information for:

• General Processing
• Direct Addressing of Memory
• Indirect Addressing of Memory
• Interrupt Control

---

General Processing Registers

STATUS Register

TO - Indicates Watch Dog Timer has expired
PD - Sleep instruction status
Z - Indicates if last instruction resulted in a 0
DC - last instruction resulted in a carry-out from the 4^th low-order bit
C - last instruction resulted in a carry-out from Most Significant Bit

WREG Register

Referred to as the Working Register or W register, WREG serves as an accumulator.

---

Direct Addressing Registers

BSR (Bank Select Register)

The lower 5 bits of BSR contains the bank number (0-31) of the active data bank. Information explaining how the BSR is used can be found in the Direct Memory Addressing section of the PIC16F1xxx tutorial

PCL and PCLATH registers
These registers are used when writing to or reading from the 15-Bit Program Counter. Information on the use of PCL and PCLATH is explained in the Program Memory section of the PIC16F1xxx tutorial

---

Indirect Addressing Registers

INDF0, FSR0L, FSR0H ,
INDF1, FSR1L, FSR1H
These six registers control the two indirect addressing channels on the MCU. The details of using these registers is provided in the Indirect Addressing section of the PIC16F1xxx tutorial

---

Interrupt Control Register

INTCON

GIE - Global Interrupt Enable
PEIE - Peripheral Interrupt Enable
TMR0IE - Timer 0 interrupt enable
INTE - External interrupt enable
IOCIE - Interrupt on change enable
TMR0IF - Timer 0 interrupt flag
INTF - External interrupt flag
IOCIF - Interrupt on change flag

INTCON is the control register for the PIC16F1xxx interrupts. Information on using this control register can be found in the Interrupt section of the PIC16F1xxx tutorial.

---

Special Functions Registers ( SFRs)

In each of the PIC16F1xxx's data banks there are up to 20 Special Function Registers (SFRs). The SFRs are located just below the core registers starting at address xxCh. SFRs control the PIC16F1xxx peripherals , digital I/O ports , and oscillator settings.

---

General Purpose RAM

The general purpose RAM is located on each memory bank just below the SFRs. This memory is available for application data.

---

Common RAM

The last 16 bytes of bank 0 (addresses 70h - 7Fh) are repeated on every data bank. This allows application programs to access variables located in these addresses without having to set BSR.

---

Shadow Registers

Located in the bottom of bank 31 are the PIC16F1xxx shadow and stack registers. The shadow registers save the program's context by capturing several core registers when an interrupt occurs. The core registers are restored when a RETFIE (return from interrupt) instruction is executed. More information on the shadow registers can be found in the interrupt section of the PIC16F1xxx tutorial.

The stack is used to store the Program Counter in the event of an interrupt or subroutine call. Information on the stack and the associated registers can be found on the programmer's model section of the PIC16F1xxx tutorial