PIC16F1xxx Instruction Set

This applies to the PIC16F1xxx and PIC16LF1xxx families of PIC MCUs.

Byte Oriented Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
ADDWF f,d Add W and f 1 00 0111 dfff ffff C, DC,Z 2
ADDWFC f,d Add with Carry W and f 1 11 1101 dfff ffff C,DC,Z 2
ANDWF f,d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f,d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f,d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f,d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 1fff ffff Z 2
CLRW Clear W 1 00 0001 0000 00xx Z
COMF f,d Complement f 1 00 1001 dfff ffff Z 2
DECF f,d Decrement f 1 00 0011 dfff ffff Z 2
INCF f,d Increment f 1 00 1010 dfff ffff Z 2
IORWF f,d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f,d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff None 2
RLF f,d Rotate left f through Carry 1 00 1101 dfff ffff C 2
RRF f,d Rotate right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f,d Subtract with Borrow W from f 1 11 1011 dfff ffff C,DC,Z 2
SUBWFB f,d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 2
SWAPF f,d Swap nibbles in f 1 00 1110 dfff ffff None
XORWF f,d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
Byte Oriented Skip Instructions
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
DECFSZ f,d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff None 1,2
INCFSZ f,d Increment f, Skip if 0 1(2) 00 1111 dfff ffff None 1,2
Bit Oriented File Register Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
BCF f,b Bit Clear f 1 01 00bb bff ffff None 2
BSF f,b Bit Set f 1 01 01bb bfff ffff None 2
Bit Oriented Skip Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
BTFSC f,b Bit Test f, Skip if Clear 1(2) 01 10bb bfff ffff None 1,2
BTFSS f,b Bit Test f, Skip if Set 1(2) 01 11bb bfff ffff None 1,2
Literal Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move Literal to BSR 1 00 0000 001k kkkk None
MOVLP k Move Literal to PCLATH 1 11 0001 1kkk kkkk None
MOVLW k Move literal to W 1 11 0000 kkkk kkkk None
SUBLW k Subtract W from Literal 1 11 1100 kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Control Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
BRA k Relative Branch 2 11 001k kkkk kkkk None
BRW Relative Branch with W 2 00 0000 0000 1011 None
CALL k Call Subroutine 2 10 0kkk kkkk kkkk None
CALLW Call Subroutine with W 2 00 0000 0000 1010 None
GOTO k Goto address 2 10 1kkk kkkk kkkk None
RETFIE k Return from interrupt 2 00 0000 0000 1001 None
RETLW k Return, place literal in W 2 11 0100 kkkk kkkk None
RETURN k Return from subroutine 2 00 0000 0000 1000 None
Inherent Operations
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
NOP No Operation 1 00 0000 0000 0000 None
OPTION Load OPTION register with W 1 00 0000 0110 0010 None
RESET Software device Reset 1 00 0000 0000 0001 None
SLEEP Go into standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register 1 00 0000 0110 0fff None
C-Compiler Optimized
Mnemonic,
Operands
Description Cycles 14-bit Opcode
MSb……LSb
Status
Affected
Notes
ADDFSR Add Literal to FSRn 1 11 0001 0nkk kkkk None
MOVIW Move Indirect FSRn to W 1 00 0000 0001 0nnn Z 2
MOVWI Move W to Indirect FSRn 1 00 0000 0001 1nnnn Z 2

Notes

  1. If the program counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP
  2. If this instruction addresses an INDF register AND the MSb of the corresponding FSR is set, the instruction requires one additional instruction cycle.

Included page "sidebar:common" does not exist (create it now)

© 2016 Microchip Technology, Inc.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.