Memory Organization: Overview

The PIC32MX family of microcontrollers provides 4 GB of unified, virtual memory address space. There are several features of this memory system that are distinct, as compared to other PIC® Microcontrollers (MCUs):

  • Unified Address Space: Instructions and data share the same memory space
    • 'C-programming friendly' - no need for special rom or psv pointer declarations.

Although the address space is unified, PIC32MX MCUs contain multiple bus interfaces to allow concurrent instruction and data access, thus, implementing a Harvard style hardware bus architecture, similar to existing 8-/16-bit PIC® MCUs.

  • Virtual Memory Addressing

All MIPS-based CPUs implement 2 address spaces: a virtual address space, consisting of all the addresses that can be used in a program and a physical address space, consisting of all the addresses that can be sent out on the address bus. Virtual addresses are mapped (translated) to physical addresses by the memory management unit (MMU).

  • Multi-Layer System Bus

To Summarize: Addresses in the PIC32MX are:

  • Issued as virtual addresses by the MIPS core, then
  • Mapped into physical addresses by the MIPS memory-management-unit (MMU), then
  • Mapped into a bus address via the system bus matrix, and finally
  • Used to select the appropriate peripheral or location in Data SRAM

Other key features of PIC32MX memory organization include the following:

  • 32-bit native data width
  • Separate User and Kernel mode address spaces
  • Flexible program Flash memory partitioning
  • Flexible data RAM partitioning for data and program space
  • Separate boot Flash memory for protected code
  • Robust bus-exception handling to intercept runaway code
  • Simple memory mapping with Fixed Mapping Translation (FMT) unit
  • Cacheable and non-cacheable address regions

Please refer to PIC32MX Family Reference Manual Section 3. Memory Organization (DS61115F) for detailed coverage on the memory organization and configuration.

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