System Bus Matrix
system-bus-matrix-overview-v2.png

The PIC32MX family of devices incorporates a System Bus Matrix, which is implemented as a multi-layer fabric that allows concurrent transactions by multiple initiators (bus masters) to multiple targets (bus slaves). There are no arbitration delays unless two initiators attempt access to the same target at the same time. Initiators include the CPU, general purpose DMA, and bus master peripherals with dedicated DMA access.

Main Features

  • Runs at SYSCLK speed (100MHz max)
  • Multiple initiators talk to multiple targets
  • Up to three independent transactions per SYSCLK cycle
  • Arbitration takes place for collisions

Advanced features of the Bus Matrix Module, such as RAM/Flash memory access allocation will not be discussed here.

  • You can leave those BMX registers at their default values, which by default allocates all RAM and Flash memories for Kernel mode applications (as shown on the PIC32MX Memory Map).


If you want to run code from RAM or set up User mode partitions, you will need to configure those specific BMX registers.

Refer to Section 3 of the PIC32MX family reference manual (Memory Organization - DS61115) for a detailed discussion of these features.

Initiators & Targets

The Bus Matrix connects master devices, generically called initiators, to slave devices, generically called targets. The PIC32MX product family can have up to five initiators and three targets (e.g., Flash, RAM, etc.) on the main bus structure, as shown here:

initiators-and-targets.png

Of the five possible initiators, the CPU Instruction Bus (CPU IS), CPU Data Bus (CPU DS), In-Circuit Debug (ICD) and DMA Controller (DMA) are the default set of initiators and are always present. The PIC32MX also includes an Initiator Expansion Interface (IXI) to support additional initiators for future expansion.

The Bus Matrix decodes a general range of addresses that map to a target. The target (memory
or peripherals) may provide additional addresses depending on its functionality. The following table lists the targets which the initiators can access:

initiator-access-map.png

Note: Some peripherals are grouped together as a single target to form a Peripheral Bus, which in addition to sharing a target interface, also shares a common peripheral bus clock source (PBCLK).

System Bus latency is therefore determined by:

  • Speed of the target peripheral/bus
  • Collisions/Arbitration Policy

System Bus Matrix Arbitration

Since there can be more than one initiator attempting to access the same target, an arbitration scheme must be used to control access to the target. The arbitration modes assign priority levels to all the initiators. The initiator with the higher priority level will always win target access over a lower priority initiator.

A variety of "fixed-priority" arbitration modes are provided. These modes are controlled by the BMXCONBMXARB<2:0> settings. The default setting (0x001) selects Arbitration Mode 1, which enables the following priority assignment:

arbitration-mode-1.png

A detailed discussion of arbitration settings is beyond the scope of this tutorial. Refer to Section 3 of the PIC32MX family reference manual (Memory Organization - DS61115) for a detailed discussion.

Bus Error Exceptions

The Bus Matrix generates a bus error exception on:

  • Any attempt to access unimplemented memory
  • Any attempt to access an illegal target
  • Any attempt to write to program Flash memory

Bus Error Exceptions may be temporarily disabled by clearing the BMXERRxxx bits in the BMXCON register, which is not recommended. The Bus Matrix disables bus error exceptions for accesses from CPU IS and CPU DS while in DEBUG mode.

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