Instruction Categories

CPU Instructions

MIPS32® Release 2 CPU instructions are organized into the following functional groups:

  • Load and Store: Used to load/store operands from memory to/from the GPR.
  • Computational: Arithmetic, Logic and Shift operations performed on integers represeneted in 2's complement format
  • Jump and Branch: Instructions that modify the Program Counter (PC)
  • Miscellaneous: Exception handling, Conditional move, Cache Prefetch, NOP
  • Coprocessor: Instructions that deal with the coprocessor units

The following table provides some example assembly language mnemonics for these categories:

cpu-instructions.png

MIPS32® Release 2 CPU Instructions are fully documented in MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set (Document MD00086-2B-MIPS32BIS-AFB-05.04) available here.

DSP Instructions

PIC32 MZ devices with microAptiveTM or M5150 Core implement MIPS® DSP ASE Revision 2 instructions. They are classified into the following categories:

  • Arithmetic: Instructions that perform addition/subtraction of Q15/Q31 data
  • GPR-based shift: Logical/Arithmetic shift operations on DSP data
  • Multiply/Multiply-Accumulate: MAC operations on DSP data
  • Bit manipulation: Specialized DSP bit operations
  • Compare-Pick: Element-wise comparisons
  • DSP Control Access: Instructions that access the DSP Control Register and Accumulators
  • Indexed-Load: Indexed load sub-class
  • Branch: Specialized branch operation

The following table provides some example assembly language mnemonics for these categories:

dsp-instructions.png

The DSP instruction set is nothing like the regular and orthogonal MIPS32® instruction set. It's a collection of special-case instructions, aimed at known hot-spots of important DSP applications.

MIPS® DSP ASE Revision 2 DSP Instructions are fully documented in MIPS® Architecture for Programmers
VolumeIV-e: The MIPS® DSP Module for the MIPS32® Architecture (Document MD00374-2B-MIPS32DSP-AFB-02.41)

Floating Point Unit (FPU) Instructions

PIC32 MZ devices with M5150 Core implement MIPS64®Floating Point Unit instructions. They are classified into the following categories:

  • Data Transfer: Instructions for moving data to/from the FPU
  • Arithmetic: Operations on formatted data values
  • Conversion: These instructions perform conversions between floating point and fixed point data types
  • Formatted Move: Move formatted operand values among FPU general registers
  • Conditional Branch: PC-relative conditional branch instructions that test condition codes set by FPU compare instructions
  • Miscellaneous: Conditionally move one CPU general register to another, based on an FPU condition code

The following table provides some example assembly language mnemonics for these instruction categories:

fpu-instructions.png

For more information on the FPU instruction set, please refer to chapter 12 in the PIC32MZ family reference manual Section 50. CPU for Devices with MIPS32® microAptiv™ and M-Class Cores

Macro Instructions

Most MIPS® assemblers will synthesize a set of macro (also called synthetic or pseudo) instructions intended to simplify the task of writing MIPS® assembly language programs.

Every time a programmer specifies a macro instruction, the assembler replaces it with a set of actual MIPS® instructions to accomplish a task.

For example, let us suppose a programmer used the load-immediate (li) macro instruction to load a 32-bit constant into a register:

The MIPS® assembler would then insert the following two MIPS® instructions to accomplish the task:

Some pseudo-instructions require a temporary register for intermediate calculations. Assemblers use register at for this purpose.

The mere existence of "macro" assembly instructions should be a warning sign to budding MIPS® assembly language programmers - MIPS® machine code might be rather dreary to write!

This article provides a list of commonly synthesized pseudo-instructions.

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