CPU Registers

The MIPS32® Architecture defines the following CPU registers:

  • Thirty-two 32-bit general purpose registers (GPRs)
  • A special-purpose program counter (PC) that is affected only indirectly by certain instructions and is not architecturally visible
  • One 64-bit Accumulator to hold the results of integer multiply, divide and multiply-accumulate operations (HI and LO)

The MIPS® DSP ASE revision 2 adds three additional HI/LO registers to create a total of four accumulator registers (ac0-ac3).

Many common DSP computations involve accumulation (e.g., convolution). MIPS® DSP ASE Revision 2 instructions that target the accumulators use two bits to specify the destination accumulator, with the zero value referring to the original accumulator of the MIPS® architecture.

The MIPS64® FPU adds 32-64bit registers to the register set.

MIPS64® FPU performs ANSI/IEEE 754 compliant single and double precision floating point arithmetic operations in hardware.

microAptivTM MPU Core CPU Register Set


M5150 MPU Core CPU Register Set


General Purpose Registers

The MIPS architecture has 32 general purpose CPU registers for your program use: $0 - $31.

Two, and only two, behave differently than the others: $0 & $31:

  • $0 - Always returns zero, no matter what you store in it.
  • $31 - Always used by the normal subroutine calling instruction (jal)

The remainder are identical and may be used in any instruction to hold data or addresses.

Although the hardware makes few rules about the use of registers, their practical use is governed by conventions that have been developed over time in order to facilitate code re-use.

With the conventional uses of the registers come the conventional set of names. The following table lists the conventional names of the registers with usages (from the MPLAB® XC32 Users Guide DS50001686G):


HI(x)/LO(x) (ac0-ac3) Register Usage

  • During a legacy multiply operation (mult), the HI and LO registers store the product of integer multiply. Special instructions are available to move HI/LO results to/from the register file (mfhi, mflo, mthi, mtlo)

MIPS32® Release 3 added a mul instruction that moves the lower half of the result directly to GPR, increasing the throughput of multiply-intensive operations.

  • Multiply-Add (madd) and Multiply-Subtract (msub) produce a full-width product twice the width of the input operations and adds or subtracts the product from the concatenated value of HI and LO. The low half of the addition is loaded into LO and the high half is loaded into HI.
  • Divide (div) produces a quotient that is loaded into LO and a remainder that is loaded into HI.
  • Three additional HI/LO registers are available to create a total of four accumulator registers. Many common DSP computations involve accumulation (e.g., convolution). MIPS® DSP ASE Revision 2 instructions that target the accumulators use two bits to specify the destination accumulator, with the zero value referring to the original accumulator of the MIPS® architecture.

Floating Point Unit (FPU) Register Usage

MIPS64® FPUs have 32 floating point registers, usually referred to as $f0-$f31. Each is a 64-bit register capable of holding a double-precision value.

  • The FPU has a separate pipeline for floating point instruction execution. This pipeline operates in parallel with the integer core pipeline and does not stall when the integer pipeline stalls. This allows long-running FPU operations, such as divide or square root, to be partially masked by system stalls and/or other integer unit instructions.
  • The FPU access is provided through Coprocessor 1. Like the main processor core, Coprocessor 1 is programmed and operated using a Load/Store instruction set. The processor core communicates with Coprocessor 1 using a dedicated coprocessor interface.
  • The FPU functions as an autonomous unit. The hardware is completely interlocked such that, when writing software, the programmer does not have to worry about inserting delay slots after loads and between dependent instructions.
  • FPU registers are accessed via a dedicated FP instruction set, which provides operations in the following categories:
    • Load/Store: Moving data directly between FPU registers and memory
    • Register-Register Move: Data movement between FP and general purpose registers
    • Three-Operand Arithmetic Operations: The regular add, multiply and so on.
    • Multiply-Add Operations: Used for DSP algorithms
    • Sign-Changing
    • Conversion Operations: Conversion between single, double and integer values
    • Conditional Branch and Test Instructions

For more information on the FPU, please refer to chapter 7 in See MIPS Run Linux by Dominic Sweetman, as well as PIC32MZ family reference manual Section 50. CPU for Devices with MIPS32® microAptiv™ and M-Class Cores

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