microAptive® MPU Core ISA: Overview

The Instruction Set Architecture (ISA) of a Central Processing Unit (CPU) refers to the lowest-level interface between the programmer and the CPU, and includes the following aspects:

  • Data types
    • Supported operand representations
  • Operations on data
    • Arithmetic/other operations that can be performed on the operands
  • Instruction format
  • Memory organization
  • Addressing modes

ISAs are also often referred to as the "Programmers Model" of a CPU

PIC32MZ, with the MIPS32® microAptiv™ MPU core implements Release 2 of the MIPS32® architecture in a 5-stage pipeline. It includes support for the microMIPS™ ISA.

PIC32MZ, with the MIPS32® M-Class M5150 MPU core implements Release 5 of the MIPS32® architecture in a 5-stage pipeline, in addition to the features supported by the microAptiv™ core ISA.

These ISAs are classified as Load/Store or Register-Register type (i.e. ALU operations act on register operands only - no memory references). On modern CPUs, this is done to decouple CPU speed from main memory speed.

Refer to Imagination Technologies "MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture" for more information on the CPU Programming Model for the MIPS32® core.

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