This chapter is intended to provide you with basic knowledge of driving MOSFETs in simple circuits. You will investigate when it is appropriate to directly drive a MOSFET versus using a MOSFET Driver integrated circuit. Guidance is also provided in designing gate drive circuits for various applications.
3.1 Prerequisites
- Chapter 1 - Getting Started with the MPLAB® Mindi™ Analog Simulator
- A review of the TC4427 Datasheet
3.2 MOSFET Driving Experiments
For these exercises, the gate of the MOSFET is viewed as a capacitive load. This gate capacitance is a parasitic effect proportional to the die size of the MOSFET. As the capacitance increases, the time required to fully charge the capacitor increases, resulting in slower switching times and potentially greater losses. A MOSFET driver can be used to provide greater drive current and/or higher voltages to optimize system parameters.
The goal of these case studies is to understand when using a MOSFET Driver is beneficial to your circuit and how to implement a simple, robust MOSFET gate drive solution. Later studies will cover tuning of gate drive circuits to adjust circuit timing, as well as control of transients due to parasitics.
3.3 Case Study: Basic Gate Drive Circuits
The most basic form of MOSFET gate drive circuit is an output directly from a micro-controller or PWM controller. In many low-power, low-frequency applications, this method is cheap, simple, and robust. Some potential shortcomings of this approach include:
a
Limited source and sink current
- Increasing available current for charging the MOSFET’s gate produces faster switching times, reducing losses
- Removing the burden of the gate drive power losses from the controller keeps the controller cooler
b
Limited gate drive voltage
- Many controllers are limited to a 3.3 V or 5 V output
- Increased gate drive voltages result in lower MOSFET on-resistances
c
Increased trace inductance
- It may be challenging or undesirable to have the controller placed close to the MOSFETs, resulting in long gate drive traces
- Increased inductance can increase switching times, as well as produce ringing which can cause electrical overstress
Utilizing a MOSFET Driver IC in series between the controller and the MOSFET can provide many advantages, giving you a vast selection of drive voltage and peak current levels, as well as reducing gate drive circuit inductance by allowing closer proximity of the driver and MOSFET.
3.3.1 Direct Drive Simulation Examples
a
Open the simulation MASTERS_Drivers_Direct.wxsch example by navigating to the MPLAB® Mindi™ Self-Paced Workbook Website.
b
Download the file named Chapter03.zip.
c
Unzip the folder to a known location and open MASTERS_Drivers_Direct.wxsch which is depicted below.
This simulation example is a simple boost converter circuit, where the ground referenced MOSFET is being driven by an output of a microcontroller or PWM controller. The boost converter circuit is open-loop for simplicity, and converts a 12 V input into an approximately 24 V output. The load resistance is 12 Ω, which will result in a ~2 A load. The switching frequency is set to 100 kHz.
After running the simulation, observe these various signals:
a
Drain-to-Source voltage of Q2, focusing on looking for overshoot/undershoot.
b
Gate voltage of Q2, focusing on the rise and fall times of the gate drive signal.
c
Gate drive current through resistor R3, focusing on peak source and sink currents.
d
Efficiency of the power-train, examined by using the Efficiency Calculator tool.
3.3.2 TC4427 MOSFET Driver Simulation Examples
a
Open the TC4427 application schematic under MOSFET and Motor > Low-Side > TC4427, as seen in the figure below.
The difference with the previous schematic is that a TC4427 MOSFET Driver was inserted in series between the controller and the MOSFET. A screenshot of the schematic is shown in the next figure.
b
To ensure accurate comparisons between the direct-drive example and this example, set the MOSFET (Q1) to IRL520N, the load resistance (R1) to 12 Ω, and the external gate resistance (R3) to 2 Ω.
After running the simulation, observe these various signals:
c
Drain-to-Source voltage of Q2, focusing on looking for overshoot/undershoot.
d
Gate voltage of the MOSFET Q2, focusing on the rise and fall times of the gate drive signal.
e
Gate drive current through resistor R3, focusing on peak source and sink current values.
f
Efficiency of the power-train, examined by using the built-in Efficiency Calculator tool.
Be sure to note the differences in rise time and fall time, as well as peak current, and efficiency when comparing the direct drive results to the TC4427 schematic results.
When all of the signals above have been investigated, replace the IRL520N MOSFET with the IRL530N MOSFET. It is important to note that the CISS value (Input Capacitance) for the IRL530 MOSFET is approximately double that of the IRL520N MOSFET, so the load on the gate drive circuit will be doubled. Observe the same signals and note how they compare to the previous values. Note if the efficiency has improved as well.
3.4 Case Study: Gate Drive Circuit Tuning
When is gate drive circuit tuning recommended?
There are always tradeoffs in circuit design and gate drive circuits are no exception. Driving MOSFETs faster using a strong gate drive can result in large transient voltages and ringing. Transients and ringing can usually be attributed to parasitics within the circuit such as packaging inductance, PCB trace inductance, parasitic capacitances, etc. These transients can lead to increased noise, as well as device damage if transients cause electrical overstress to a component.
In order to limit the severity of the transients, a resistor is commonly placed between the output of the MOSFET driver and the gate of the MOSFET. Note that this resistor is present on the simulation schematics used in the previous case study (R3). Selecting a value for this resistor is usually the result of experimentation with the actual hardware, and it can range from 0 Ω to over 100 Ω depending on the application and circuit parasitics. In some cases, it may be desired to have different amounts of gate damping resistance in the turn-on and turn-off paths. This can be accomplished by placing a diode and resistor parallel to the gate resistor.
In order to see the effects of various system parasitics, the MASTERS_Drivers_TC4427.wxsch simulation schematic can be modified as follows:
a
Add parasitic inductances at all terminals of Q2, as seen in the figure below. As a starting point, 10 nH can be used for all parasitic inductances.
b
Run the schematic and note the overshoot at the Drain-to-Source voltage of Q2.
c
Change the values of the parasitic inductances around the MOSFET, as well as the values of the damping resistors in the gate drive path, and re-run the schematic. The goal of this exercise is to see how parasitics that result from packaging, PCB layout, etc. can affect transients in the circuit.
3.5 References
a
Datasheets
b
Evaluation boards
c
Application notes