Leakage Currents

Leakage currents cause voltage drops when they flow through either resistors or parasitic resistances. This section focuses on parasitic resistances presented by the Printed Circuit Board (PCB): surface resistance and bulk (through the dielectric) resistance. Leakage currents cause voltage ramps when they flow into a capacitor. Common examples are the gain capacitor of a transimpedance amplifier and the non-inverting input of an op amp with no DC path to ground (not recommended).

Op amp leakage (bias) currents: AN1177, Op Amp Precision Design: DC Errors

High Impedance Sources

High impedance signal sources are susceptible to errors caused by leakage currents. These sources are usually modeled as a current source with high parallel resistance (a Norton model):


One sensor that is modeled as a Norton current source is the photodiode. A common op amp circuit used for photocurrent measurements is the transimpedance amplifier.

Sometimes, high impedance sources are modeled as a voltage source with a high series resistance (a Thevenin model):


The pH electrode is one example with a Thevenin source. A common op amp implementation is a noninverting amplifier.

PCB Surface Leakage

Parasitic Surface Resistance

Surface contamination on a PCB creates resistive paths for leakage currents. These leakage currents can cause appreciable voltage shifts, even in well-designed circuits. The contamination can be humidity (moisture), dust, chemical residue, etc.

On a PCB, leakage currents flow on the surface, to a sensitive node (high resistance), from nearby bare metal objects (including traces) at a different voltage. To model sensitivity to surface contamination in your circuit, add resistors between the high impedance node and other nearby nodes. For example, the figure below shows an amplifier circuit with a Thevenin source (VS and RS). Since RS is high and the amplifier’s input is high impedance, VIN is a high impedance node. Parasitic resistances (RP1 to RP4) are connected to all other (nearby) voltage nodes (traces on a PCB), including ground. RP1 to RP4 are open-circuited for most design work. For leakage current design calculations, they take on high resistance values (usually one at a time).


The figure below shows an amplifier circuit with a Norton source.


The parasitic resistor values (RP) depend on your PCB layout. For a typical layout, with today’s geometries (traces are close and short) and materials, we have:

  • RP ~ 1,000 GΩ, low humidity, and contamination
  • RP ~ 1 GΩ, high humidity, and contamination

These RP values need to be modified for atypical geometries; see PCB Parasitic Resistance. These RP values also need to be modified for the worst-case conditions for your application. Measurements in your conditions, and with your PCB layout, will give better estimates of RP.



A standard PCB clean step helps minimize surface contamination, but may not eliminate the problem. An additional cleaning step, using isopropyl alcohol, is needed to clean the residue left by some PCB cleaning solvents. This can then be blown dry using compressed air (with an in-line moisture trap).


In order to maintain the PCB cleanliness after the initial clean, you may coat the PCB surface. The coating needs to be a barrier to moisture and other contaminants; solder mask, epoxy and silicone rubber are examples. The coating will have internal (bulk) leakage currents; this effect needs to be evaluated for your design.

Guard Rings

Guard rings surrounding critical signal traces, when properly applied, can significantly reduce PCB surface leakage currents into critical (high resistance) nodes. These guard rings have no solder mask so that the leakage currents flow into them, instead of into the sensitive trace. The guard ring is biased at the same voltage as the sensitive node; it needs to be driven by a low impedance source. Guard rings increase the capacitance at critical nodes. Since they are driven by low impedance sources, these capacitances have little effect on performance.

Unity Gain Buffer

The figure below shows a unity gain buffer with a guard ring. This guard ring is biased by VOUT and protects (surrounds) the op amp’s non-inverting input (and all top metal connected to it) on the PCB surface. The diagram is for surface mount components only. RN is an 0805 SMD to give sufficient clearance for the guard ring trace between its pads.


The parasitic resistances are connected as shown in the figure below. RP2 injects current into U1’s non-inverting input (the high impedance node). The other parasitic resistors inject current into the guard ring, which is driven by VOUT; they do not affect the performance. The voltage across RP2 is U1’s offset voltage (VOS), so the leakage current is greatly reduced. For instance, if V,, ≤ ±2 mV and the voltage without the guard ring is 2 V, the leakage current would be reduced by a factor of about 1,000.


One example of an application that sometimes uses unity gain op amps are pH meters. In that case, however, both VIN and RN are located off the PCB; the guard ring only needs to surround U1’s non-inverting input.

Non-inverting Gain Amplifier

The figure below shows a non-inverting gain amplifier with a guard ring. This guard ring is biased by VOUT, RF and RG; it protects (surrounds) the op amp’s non-inverting input (and all top metal connected to it) on the PCB surface. RF and RG are low impedance, to drive the guard ring properly. RN is a low valued resistor that cancels thermojunction voltage effects but has little effect on bias current errors (e.g., IBRN « ±1 mV).


The parasitic resistances are connected, as shown in the figure below. Similar to the Unity Gain Buffer in the last section, U1’s offset voltage (VOS) is across RP2, which greatly reduces its leakage current. The other parasitic resistances are driven by VOUT, RF and RG; they do not affect the performance. The leakage current is typically reduced by a factor of about 1,000.


Transimpedance Amplifier

The figure below shows a photo-diode at the input of a transimpedance amplifier, with a guard ring. This guard ring is biased at ground; it protects (surrounds) the op amp’s inverting input (and all top metal connected to it) on the PCB surface. RF is highly valued for the DC gain (VOUT/ID1).


The parasitic resistances are connected as shown in the figure below. Similar to the Non-inverting Gain Amplifier in the last section, U1’s offset voltage (VOS) is across RP1, which greatly reduces its leakage current. The other parasitic resistances are connected to ground; they do not affect the performance. The leakage current is typically reduced by a factor of about 1,000.


Guard Rings on Both PCB Surfaces

For op amps in through-hole packages (e.g., PDIP), guard rings are needed on both top and bottom surfaces. The same design principles apply to both surfaces.

Any jumper traces (via to other surfaces, trace and via back to the original surface), connected to traces with guard rings, also need guard rings around the jumper traces. It is better, when possible, to avoid jumper traces for critical nodes.

PCB Bulk Leakage

The dielectric material used in a PCB (e.g., FR4) is an insulator. Its resistance to leakage currents through the bulk (the dielectric) is described by its volume resistivity (ρV). ρV values vary considerably, depending on the dielectric and on ambient conditions. Usually, bulk leakage currents are much smaller than surface leakage currents; they can be neglected in many designs. Designs that minimize surface leakage currents, however, may be affected by bulk currents. The example below shows one example of how bulk leakage currents occur. Two traces run in parallel and are separated by the dielectric. The leakage current between the traces, flowing through the dielectric, is modeled by a parasitic resistor (see RP1 in the figure below).


Any two metal areas on the PCB (on a surface or buried in an inner layer), at different potentials, will have a leakage current between them. The value of the parasitic (bulk) resistance depends on:

  • The geometry of the areas
    • The distance between
    • The cross-sectional area is seen by the current
  • Nearby metal objects (e.g., a guard ring) that modify the current flow path
  • The volume resistivity (ρV)
    • Dielectric material
    • Exposure to chemicals (e.g., water)

The following discussion shows simple techniques to minimize these leakage currents. See Appendix B: “PCB Parasitic Resistance” for ways to estimate bulk leakage currents.


Moving traces to the surfaces, from inner layers, increases the distance between them (e.g., the example of parallel traces above). The example below shows two parallel traces, with a distance separating them. This extra distance increases the parasitic resistance.


Crossed Traces

When two traces must cross, place them on opposite surfaces and in normal directions to minimize the parasitic resistance; see the example below.


Guard Rings

The example below shows a trace on the left (node 1), a guard ring (node 2), and a sensitive trace (node 3). The guard ring provides a low resistance path that redirects some of the current between node 1 and node 3 to itself. RPB2 in the figure below acts as an attenuator to the input voltage (V1). When V2 ≈ V3, the parasitic current (into V3) is significantly reduced.


Guard Plane

The example below shows a trace on the left (node 1), a guard plane (node 2), and a sensitive trace (node 3). The guard plane behaves similar to a guard ring, except that it forms a distributed attenuator to the input voltage (see the figure below); this attenuation can be much greater.


Dielectric Material

Changing the dielectric material changes its bulk resistivity (ρV) and susceptibility to humidity. For designs that need exceptional performance, this is an option worth exploring.

Moisture Control

When a dielectric is exposed to moisture for an extended period of time, it can become wet. This reduces its bulk resistivity (ρV). Measures to control exposure to moisture reduce this effect. One possibility is the use of coatings.

Isolating Sensitive Nodes

Another way to minimize PCB leakage currents is to isolate sensitive nodes (wires, package pins, etc.) from the board (i.e., not touching).

One approach is to use teflon stand-offs. This has technical advantages, but can be costly to implement. Another approach is to keep sensitive nodes in the air. Bending package leads and routing holes in the PCB are possible techniques to accomplish this.

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