dsPIC® ADC Applications

Some of the dsPIC® digital power conversion applications, such as Power Factor Correction (PFC), and Full-Bridge Zero Voltage Transition (ZVT) Converter are covered on the Power Operations page. The following section covers a digital power conversion application, specifically on the Boost Converter, in relation to using dsPIC® DSC ADC.

dsPIC® DSC Boost Converter Application

A Boost Converter is one of the most popular DC/DC Converter topologies. A boost converter steps up voltage from a lower rectified input voltage to higher regulated output voltage. The figure below illustrates the concept of the boost converter using an inductor (L), switch, diode (D) and the output capacitor (Co).

boost-concept.png

Below we see a practical example of using a dsPIC33FJ32GS406 in a boosted Power Factor Correction (PFC) converter application.

boost-adc.png

Note:
K1, K2 and K3 are feedback gain circuits for the ADC channels. K1 is used to measure the AC-input voltage, which is used for generating a sinusoidal current reference. K2 is used for sensing the inductor current and K3 is used for sampling the output voltage. The gain circuits interface with the analog inputs of the dsPIC® and are configured to sample simultaneously. A conversion is triggered on all three ADC analog inputs once every 3 PWM cycles and the current loop is executed after every conversion. The voltage loop is executed only once every 15 current loop executions. See “Switched-Mode Power Supply (SMPS) AC-to-DC Reference Design Schematics” for detailed schematics.

Just like the boost converter, the boost PFC converter produces a voltage higher than the input rectified voltage. Therefore, the switch (MOSFET) should be rated higher than the output voltage. The figure below shows the Boost PFC input current shape.

pfc-boost-current-voltage.png

PFC Theory

Most of the power conversion applications consist of an AC-to-DC conversion stage immediately following the AC source. The figure below shows a high level block diagram of the Switched-Mode Power Supply (SMPS) AC-to-DC conversion design.

ac-dc-design.png

Since many applications demand a DC voltage source, a rectifier with a capacitive filter is necessary. Current pulses with high peak amplitude are drawn from this rectified voltage source. Please refer to the input current waveform of the PFC boost converter above. The current drawn is of short duration regardless of the load connected to the system and discontinuous. When this type of current is drawn from the mains supply, the resulting network losses, the total harmonic content, and the radiated emissions become significantly higher. At power levels of more than 500 watts (W), these problems become more pronounced. This leads to the implementation of the Power Factor Correction (PFC) using dsPIC® DSC. Because Power Factor (PF) is a parameter that gives the amount of working power used by any system in terms of the total apparent power.

Power Factor becomes an important measurable quantity because it often results in significant economic savings. The waveforms of the current with and without PFC are shown below. These waveforms show that the PFC can improve input current drawn from the main supply and reduce the DC voltage ripple. The results of these are energy consumption reduction, and increase in the power efficiency. Without PFC, the ratio of the power factor deviates from a constant, the input contains phase displacement, harmonic distortion or both, which ultimately degrades the Power Factor.

with-without-pfc.png

In a DSC-based application, the relevant analog parameters and the control loops need to be redefined. By doing this, change-over from existing analog hardware to its digital counterpart is easier and more logical. The basic function of PFC is to make the input current drawn from the system sinusoidal and in-phase with the input voltage. The figure below shows the component blocks required for PFC and the PFC stage interfaced to a dsPIC® DSC device. This is an AC-to-DC converter stage, which converts the AC input voltage to a DC voltage and maintains sinusoidal input current at a high input Power Factor. As indicated in the block diagram, three input signals are required to implement the control algorithm.

pfc-block-diagram.png

The high-speed 10-bit ADC module converts the analog inputs in pairs. This module supports up to 24 external analog inputs and two internal analog inputs. To monitor the reference voltages, two internal inputs: AN24 and AN25, are connected to the external reference source (EXTREF) and internal band gap voltages (1.2V), respectively. The 26 analog inputs available on the ADC module are grouped into thirteen analog input pairs. Each analog input pair is a combination of an even and odd numbered analog input, such as AN0 and AN1, AN2 and AN3, and so on. The technique of using pairs is particularly useful in power conversion applications that require voltage and current measurements for each PWM control loop.

The first four even numbered analog inputs in both single and dual SAR devices have a dedicated Sample & Hold (S&H) circuit. For example, the dedicated S&H circuit (SH0) samples AN0 (see figure below). On a conversion request, the dedicated S&H circuit allows the corresponding analog input to be sampled without any latency (zero latency).

adc-two-sar.png

In the boost circuit (see figure below), the dedicated S&H circuit samples the peak inductor current measurement with zero latency. Any latency in sampling would lead to an incorrect result.

adc-boost-current-measurement.png

ADC Interrupt Service Routine

The ADC Interrupt Service Routine (ISR) is the heart of the control algorithm. All control loops are executed in the ISR. Since faster control loop execution is desired for the best system performance, functions executed in this routine, as well as other time-critical functions are usually written in Assembly language. On the other hand, the main loop, peripheral setup routines, and initialization routines are written using in C.

In terms of execution priority, the ADC ISR has the highest priority for execution. The ADC module is configured to generate interleaved interrupt requests in order to execute multiple control loops within the same ISR. The flowchart below shows the SMPS AC-to-DC reference design following a single basic structure.

control-flow-chart.png

ADC Module Registers

The following lists the specific functions of the high-speed 10-Bit ADC module registers:
Register Name Descriptions
ADCON: ADC Control Register This register configures the sample conversion sequence, enables the ADC module, and is used to set up the clock divider for the ADC clock.
ADSTAT: ADC Status Register This register contains the Pair Data Ready (PxRDY) flag to indicate the analog input pair that caused the common ADC interrupt. The Pair Data Ready flag is cleared in the specific pair handler.
ADBASE: ADC Base Register(1,2) This register contains a unique offset value based on the analog input pair that caused the common ADC interrupt. It is read in the common ADC interrupt to branch to the specific analog pair handler.
ADPCFG: ADC Port Configuration Register This register configures the analog input pins as analog inputs or digital I/O.
ADPCFG2: ADC Port Configuration Register 2 This register configures the analog input pins as analog inputs or digital I/O.
ADCPC0: ADC Convert Pair Control Register 0 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 0 and Pair 1.
ADCPC1: ADC Convert Pair Control Register 1 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 2 and Pair 3.
ADCPC2: ADC Convert Pair Control Register 2 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 4 and Pair 5.
ADCPC3: ADC Convert Pair Control Register 3 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 6 and Pair 7.
ADCPC4: ADC Convert Pair Control Register 4 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 8 and Pair 9.
ADCPC5: ADC Convert Pair Control Register 5 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 10 and Pair 11.
ADCPC6: ADC Convert Pair Control Register 6 This register selects the trigger source, enables the common ADC interrupt, and allows software trigger generation for Analog Input Pair 12.

Note:
Not all control registers are available on all devices. Please refer to the specific device data sheet for more information.

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