Intelligent Power Peripheral (IPP)

What is Intelligent Power Peripheral (IPP) in dsPIC® DSC

In the previous sections, we discussed the ADC, PWM, and Comparator in detail. This section summarizes all three and we collectively call them the Intelligent Power Peripheral (IPP).

What is IPP?

IPP is a fundamental operation of SMPS devices. It is made up of traditional peripherals, and consists of several important features:

  • Each peripheral by itself (PWM, ADC, Comparator) can be independently operated.
  • These three peripherals (ADC, PWM, Comparator) work together to implement closed-loop control.
  • Hardware interconnections between them permit the system to replicate similar functionalities of analog chips with the advantage of run time change of the control parameters, if needed.

IPP characteristics

  • The PWM peripheral is capable of generating a number of different trigger signals to start the ADC operation. This synchronization allows the designer to precisely select the instant in time when the input signal should be cached. This is important because it allows you to easily implement the average current control loop.
  • When different PWM signals are generated, the PWM can interleave the generation of ADC triggers (reading currents/voltages on multiple converters) in order to efficiently manage the available time resources.
  • The comparator can be used to reset the PWM period, generating a variable frequency PWM signal; to shut down the active PWM output to limit the flowing current; or to check over-current/over-voltage events and in such a case to shut down the PWM output generation immediately.

The key idea is that the IPP is programmed at start up to operate in a specific mode and then, during run-time operation, no (or minimal) intervention from the CPU is required.

Triggering Using Intelligent Power Peripheral (IPP) in dsPIC® DSC

Trigger Generation: Reading Average Current

The trigger is generated by reading the average current. The figure below shows an example using a buck converter, where the IPP is used to generate a trigger. The upper waveform is the current flowing into the inductor of a buck converter. This current is also the current flowing to the output. We can see that it is formed by an average value Iave with a superimposed ripple current. This ripple current will be filtered out by the output capacitor, so that only Iave will flow into the load.

In an average current loop implementation, we want to measure the average current in the inductor and use this information to close the inner control loop. It can be shown that for continuous mode of operation, the average current value corresponds to the value at 50% of the active PWM signal. So the ideal situation would be to be able to generate the ADC trigger at this instant in time, as shown in the figure.

Recalling the trigger options from previous modules, we see that it is very easy to have the signal trigger generated at 50% of the active period. In fact, it is sufficient to store one half of the DUTY CYCLE value in the ADC TRIGGER REGISTER. The system will automatically generate the trigger at that time. As a result, the average current can be easily measured.


Trigger Generation: Reading Peak Current

IPP can also be used to generate triggers by reading the peak current. Below is an example where the comparator is used to change the operation of the PWM peripheral. In this example the current limit feature is implemented. Just like the average current example, the upper waveform is the current flowing into the buck inductor. This time, however, we want to implement the peak current mode, so that we can continuously monitor the current. When it reaches a preset value of the current limit, the PWM active period must be stopped. The current will then start decreasing to zero. In the following PWM cycle, the whole operation will be repeated. See figure below.


The comparator threshold is set in the internal DAC, the value to be stored is generated by the external voltage loop. When the inductor current matches this value, the PWM active interval is stopped. Note that the IPP hardware captures the duty cycle register in an internal register. This functionality is defined at start-up and is continuously implemented without any specific intervention by the CPU.

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