Current Limit Reset

The Power Supply PWM module in the dsPIC® DSCs is a high-speed design that supports many PWM mode operations including:

  • Standard Edge-Aligned PWM mode
  • Complementary PWM Output mode
  • Push-Pull PWM mode
  • Multi-Phase PWM mode
  • Variable Phase PWM mode
  • Cycle-by-Cycle Current-Limit PWM mode
  • Constant Off-time PWM mode
  • Current Reset PWM mode
  • Independent Time Base PWM mode

More details can be found here in the High-Speed PWM Family Reference Manual.

In the following section, we'll focus on the Current Reset PWM mode and the Current Limit function of the PWM module. Note that the above PWM modes can be configured in different operations working simultaneously.

Current Reset PWM Mode

The Current Reset PWM is a variable frequency mode where the actual PWM period is less than or equal to the specified period value. The independent time base is reset externally some time after the PWM signal has been deasserted. This is called Constant PWM On-Time mode. To operate in the PWM Current Reset, the PWM generator should be in Independent Time Base. If an external Reset signal is not received, the PWM period uses the PHASEx register value by default.

In the Current Reset mode, the PWM frequency varies with the load current. This is different than most PWM modes because the user application sets the maximum PWM period and an external circuit measures the inductor current. When the inductor current falls below a specified value, the external current comparator circuit (or internal comparator) generates a signal that resets the PWM time base counter. In Current Reset PWM mode, complementary PWM outputs are available.

The figure below shows an example of the Current Reset PWM signal, and the Timer value.


Constant Off-Time PWM Mode

The figure below shows an example of the Current Reset PWM mode called Constant Off-Time mode. The Constant Off-Time PWM mode (see figure below) is also a variable-frequency mode where the actual PWM period is less than or equal to the specified period value. The PWM time base is externally reset after the PWM signal duty cycle value is reached, and the PWM signal has been deasserted. This mode is implemented by enabling the Current Reset PWM mode and using the complementary PWM output. Note that the duty cycle in the figure represents the off time.


Current Reset PWM Mode Application Example

The figure below is an example of the Current Reset PWM mode, called Constant On-Time mode, which is a variable frequency PWM mode.


Note that this mode is not the same as cycle-by-cycle current-limit PWM mode, which will be discussed in the next section. From the figure, we can see that the PWM frequency is fixed per the time base period. The external current comparator resets the PWM counter. This causes the PWM cycle to restart early.


Current Limit PWM Mode

The PWM module can generate interrupts based on internal timing or on external signals through the current-limit and fault inputs. The Primary Time Base module can generate an interrupt request when a specified event occurs. Each PWM generator module has its own interrupt request signal to the interrupt controller. The interrupt for each PWM generator is an OR of the trigger event interrupt request, the current-limit input event or the fault input event for that module.

Current Limit Pins

The PWM module supports multiple fault pins for each PWM generator. These pins are labeled SFLTx (shared fault) or IFLTx (individual fault). The shared fault pins can be seen and used by any of the PWM generators. The individual fault pins can be used by specific PWM generators. Each PWM generator can select its own fault input source from a selection of up to 10 fault or current-limit sources. In the Fault Current-Limit Control (FCLCONx) registers, each PWM generator has control (FLTSRC<3:0>) bits that specify the source for its fault input signal.

Each PWM generator can use one pin as a cycle-by-cycle current-limit, and another pin for use as a fault input. This fault input pin can be configured to reset the Fault state every PWM cycle, or have the Fault state remain latched until the Fault state has been reset in software.

The figure below demonstrates the cycle-by-cycle current-limit operations. The cycle-by-cycle current-limit truncates the asserted programmed PWM signal (dotted blue lines) when the selected external fault signal is asserted. The PWM output values are specified by the current-limit override bits in one register. The override outputs remain in effect until the beginning of the next PWM cycle. This is sometimes used in Power Factor Correction (PFC) circuits where the inductor current controls the PWM On-Time. This is a constant frequency PWM. Note that the fault pin inputs can be used to implement either Current-Limit PWM mode or Current Reset mode.


Current Limit Interrupts

The state of the PWM current-limit conditions is available on the Current-Limit Interrupt Status (CLSTAT) bits in the PWM Control (PWMCONx<14>) registers. The figure below shows the logic diagram of the PWM Current-Limit Control. The CLSTAT bits display the current-limit IRQ flag, if the CLIEN bit is set. If current-limit interrupts are not enabled, the CLSTAT bits display the status of the selected current-limit inputs in positive logic format. When the current-limit input pin associated with a PWM generator is not used, these pins become general purpose I/O or interrupt input pins.

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