Transition to Digital ADC

Each Pulse Width Modulation (PWM) in the dsPIC33E/33F device can generate a trigger to the Analog-to-Digital (ADC) module to sample the analog signal at a specific instance during the PWM period. In addition, the High-Speed PWM module generates a Special Event Trigger to the ADC module based on the master time base. The table in Figure 1 shows the dsPIC33F device names, pin counts, memory sizes, and peripheral availability of each device. Please note the ADC module in the red box.

Figure 1

Figure 2 shows the interconnection between various registers in the High-Speed PWM module. Note the ADC module in the bottom left showing the triggering interface from the PWM generator.

Figure 2

PWM Period:

  • The PWM period value defines the switching frequency of the PWM pulses. The PWM period value can be controlled either by the PTPER/STPER register or by the Phase Shift registers, PHASEx, and SPHASEx, for the respective primary and secondary PWM outputs.
    • PHASEx register:
Figure 3
  • The PWM period can be controlled in different PWM modes:
    • Complementary, Redundant, and Push Pull modes. For detailed PWN modes and operations, please visit the "PWM Operations" article.

The High-Speed PWM module can operate in either the standard edge-aligned or center-aligned time base.

PWM Triggers

In digital power supplies, the ADC is used for the measurement of feedback signals. This means that a trigger signal is required by the ADC peripheral to start the conversion operation. This allows the user to select the correct instant in time when the voltage or current should be acquired. Because these feedback signals can have complex waveforms or high noise content, precise triggering of the ADC is important.

For the ADC module, the TRIGx and STRIGx registers specify the triggering point for the PWMxH and PWMxL outputs, respectively. An ADC trigger signal is generated when the Independent Time Base Counter (PTMRx or STMRx) register value matches with the specified TRIGx or STRIGx register value. The PWM triggers (TRIGx/STRIGx) have a resolution of 8.32 ns (for a PWM resolution of 1.04 ns). In addition to the triggers generated by the TRIGx and STRIGx settings, the ADC pairs can also be triggered by the current-limit sources of individual PWM generators and the Special Event Trigger (SEVTCMP). The Trigger Output Divider bits (TRGDIV<3:0>) in the PWMx Trigger Control register (TRGCONx<15:12>) act as a postscaler for the TRIGx register to generate ADC triggers. This allows the trigger signal to the ADC to be generated once for every one, two, three… and 16 trigger events. These bits specify how frequently the ADC trigger is generated.

Figure 4: STRIGx Register

Figure 5 introduces the available options to generate the trigger signal.

Figure 5

The first set of triggers can be generated by the PWM peripheral's Period register, with an approach that is very similar to the one used to generate the PWM period and duty cycle.

On the top right, the ADC Trigger register and a comparator are added. Please note that this diagram does not exactly replicate the true hardware, but it is provided to show the operation. The comparator continuously compares the value of the ADC Trigger register with the value of the counter, which is counting up or down. When the two values match, the trigger signal is generated and the ADC starts the sampling operation.

Each PWM generator consists of the Trigger Postscaler Start Enable Select bits, TRGSTRT<5:0> (TRGCONx<5:0>), that specify how many PWM cycles to wait before generating the first ADC trigger. The logic for ADC triggering by the High-Speed PWM module is shown in Figure 6.

Figure 6

Dual Trigger to Analog-to-Digital Converter (ADC) per PWM Period

One of the high-speed PWM module features is the Dual Trigger from PWM to ADC per PWM period. The trigger is controlled by the TRGCONx.

Figure 7

Dual Trigger Mode Bit (DTM)

  • 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger
  • 0 = Secondary trigger event is not combined with the DTM: Dual Trigger Mode bit
  • 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger
  • 0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger; two separate PWM triggers are generated


  • The DTM mode of operation allows the user-assigned application to take two ADC samples on the same pin within a single PWM cycle.

Incorrect triggering of the ADC may have a major impact on the operation of the power converter. Figure 8 demonstrates the need for precise ADC triggering. The converter example is a DC-DC boost converter with the current sensor located in series with the source pin of the power MOSFET. This configuration eliminates the need for a differential amplifier with a high common-mode voltage capability, providing a low-cost sensing solution. The trade-off is that the ADC only sees the MOSFET current. If the digital control system is configured to measure the peak current, a small delay in triggering the ADC will yield a result of 0x0000. This delay may be caused by software overhead or if the ADC is busy at the sampling instant.

Figure 8

We can see from the PWM, inductor, and resistor current waveforms in Figure 9 that the late sample of the peak inductor current causes zero ADC sampled data, which alters the boost converter's transfer function. By using the flexible ADC triggering features of the High-Speed PWM module, this guarantees that the ADC conversion is triggered exactly when needed by the circuitry.

Figure 9

Special Event Trigger

The Special Event Trigger is commonly used when all the PWM signals have the same frequency. A single trigger can be used to start the ADC operation. The High-Speed PWM module consists of a master Special Event Trigger that can be used as a CPU interrupt source and for synchronization of Analog-to-Digital conversions with the PWM time base. The Analog-to-Digital sampling time can be programmed to occur at any time within the PWM period. The Special Event Trigger allows the user-assigned application to minimize the delay between the time the Analog-to-Digital conversion results are acquired and the time the duty cycle value is updated. The Special Event Trigger is based on the Master Time Base. Figure 10 shows the Master Time Base block diagram.

Figure 10

The master Special Event Trigger value is loaded into the PWMx Special Event Compare register (SEVTCMP/SSEVTCMP). In addition, the PWM Special Event Trigger Output Postscaler Select bits (SEVTPS<3:0>) in the PWMx Time Base Control register (PTCON<3:0>) or the PWMx Secondary Master Time Base Control register (STCON<3:0>) control the Special Event Trigger operation. To generate a trigger to the ADC module, the value in the PWM Master Time Base Counter (PMTMR/SMTMR) is compared to the value in the SEVTCMP/SSEVTCMP register. The Special Event Trigger consists of a postscaler that allows 1:1 to 1:16 postscaler ratio. The postscaler is configured by writing to the SEVTPS<3:0> control bits (PTCON<3:0>). Special Event Trigger pulses are generated if the following conditions are satisfied:

  • On a match condition, regardless of the status of the Special Event Trigger Interrupt Enable bit, SEIEN bit (PTCON<11>)
  • If the compare value in the SEVTCMP/SSEVTCMP register is a value from zero to a maximum value of the PTPER/STPER register

The Special Event Trigger output postscaler is cleared on these events:

  • Any device Reset
  • When PTEN = 0 (PTCON<15>)

The configuration of the ADC Special Event Trigger is shown in the following code box.

ADC Triggers: Current Limit

The PWM active interval can be stopped by an external signal, e.g. current limit. At the same time, the trigger signal can be generated enabling the ADC to measure the current at that specific instant in time. Figure 11 shows the PWM signal stops upon the current limit event.

Figure 11

In the above example, the current-limit input signal is used as a trigger signal to the ADC, which initiates an ADC conversion process. The ADC trigger signals are always active, regardless of the state of the High-Speed PWM module, the FLTMOD<1:0> bits (FCLCONx<1:0>) or the
FLTIEN bit (PWMCONx<12>).

In addition to generating ADC triggers, the Special Event Trigger can also be used to generate the primary and secondary Special Event Trigger interrupts on a compare match event.


  • PTCON: PWMx Time Base Control Register
    • Sets the Special Event Trigger for the ADC and enables or disables the primary Special Event Trigger interrupt
  • SEVTCMP: PWMx Special Event Trigger Compare Register
    • Provides the compare value that is used to trigger the ADC module and generates the primary Special Event Trigger interrupt
  • STCON: PWMx Secondary Master Time Base Control Register
    • Sets the secondary Special Event Trigger for the ADC and enables or disables the secondary Special Event Trigger interrupt
  • TRIGx: PWMx Primary Trigger Compare Value Register
    • TRGCMP<12:0>: Trigger Control Value bits When the primary PWM functions in the local timebase, this register contains the compare values that can trigger the ADC module and generate a PWM trigger interrupt request.
  • STRIGx: PWMx Secondary Trigger Compare Value Register
    • STRGCMP<12:0>: Secondary Trigger Control Value bits(1) When the secondary PWM functions in the local timebase, this register contains the compare values that can trigger the ADC module.

ADC Sampling and Conversion

After the trigger signal is generated and the converted value is available in the ADC buffer, the sampling and conversion process begins. The slideshow that follows in Figure 12 shows a dual Successive Approximation (SAR) ADCs, using synchronous sampling and parallel conversion.


  • T1: The ADC trigger is generated.
  • T1 to T2: After the generation of the trigger signal, before the ADC can actually start sampling, a short time (latency) may be needed. This is because the CPU clock driving the generation of the trigger signal has to be synchronized with the clock that drives the ADC.
  • T2 to T3: This is the time required to sample the input signal, i.e., the time required by the internal Sample and Hold capacitor to charge to a voltage to a value that is equal to the input voltage level.
  • T3 to T4: This is the time required by the ADC to complete the conversion process.
  • At the end of conversion, an interrupt is generated by the ADC peripheral to enable the read operation, at the 50% point of the conversion process, while accessing the ADC buffer immediately after the data has been stored. This technique helps to reduce the loop delay.
  • ADC Design Guide: "Techniques that Reduce System Noise in ADC Circuits"
  • ADC Application Note: "Achieving Higher ADC Resolution Using Oversampling", AN1152
  • Browsing Application Notes

Figure 12
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