Transition to Digital PWM

PWM Generator (Analog)

A PWM signal is commonly generated in the analog domain by using op-amp comparators and oscillators which generate a periodic waveform of a fixed frequency. This periodic signal is compared with a threshold voltage (VTH). The threshold voltage comes from the output of the controller. It is an constant signal, although it will vary slowly with the sawtooth waveform frequency. The output of the op-amp is the PWM signal frequency. The figure below demonstrates the concept.

The comparator operates as follows. Its output is:

  • High when VTH is higher than the sawtooth signal.
  • Low when VTH is lower than the sawtooth waveform.

The above figure shows that the PWM signal's duty cycle is proportional to the value of the VTH. This technique of generating a PWM output waveform is called “edge aligned” because the generated waveform always becomes high at the beginning of the rising ramp, i.e. the beginning of the PWM period. The figure below shows a similar PWM signal using triangular waves as the oscillator signal. In the analog circuit implementation, the oscillator frequency is either fixed or selected through the selection of the R and C connected externally. Highly optimized circuits may require an iterative, time-consuming process to determine the best R and C values. Any change in the PWM frequency may require replacing the parts and possibly redesigning the entire system. In the digital PWM implementation, the frequency can be changed in wide ranges by changing the values of internal registers. This technique will be covered in the next few sections.


PWM Generator (Digital Edge-Aligned)

Generating a PWM signal using digital edge-aligned PWM generator. In the figure below, an internal digital counter starts counting up from zero. The clock is used to drive an Up Counter, it is normally derived from the system clock (the clock used by the processor to perform any activity). The dotted line represents the content of the counter starting from zero. Each time the counter starts from zero, the PWM output pin is set high.

PWM Period

The PWM peripheral has a PERIOD register, where the user can store a numerical value. An internal comparator is continuously comparing the value of the PERIOD register with the current value of the Up Counter, which is incrementing at each clock count. When the two values are equal, the comparator resets the counter to zero. The value in the PERIOD register then sets the PWM period (frequency).

It is possible to define the PWM frequency in terms of the PERIOD register value and clock period, as follows:

Fpwm = (Clock Period)(PERIOD register)

Note that this is a basic equation to show the fundamental operation of the system. In real peripherals, the equation may differ because of the prescalers used (to enable a longer period PWM) and/or different clock sources. However, these details do not change the basic discussion on the PWM operation. More specific information will be given in the next several sections.

PWM Duty Cycle

The process of setting the PWM duty cycle is the same as the period. The peripheral also has a second register, the DUTY CYCLE register where the user can store a number that represents the PWM active high period in terms of counter counts. A second comparator continuously checks the DUTY CYCLE register and the Up Counter content. When they match, the PWM output pin is reset, but the Up Counter is not affected and continues to count up to the PWM period. See figure below. The duration of the high interval within the PWM period can be set according to this expression below:

Active High Duration = (Clock Period)(DUTY CYCLE register)


With the correct choice of the value stored in the DUTY CYCLE register, any duty cycle can be obtained. Sometimes there are some small limitations of the minimum duty (> 0%) or max duty (<100%), but this depends on the hardware implementation.

Note that in power converters, the duty cycle value is regularly update because it is the entity that is controlled by the control loop architecture. The new value of the duty cycle may become available at any instant within the PWM period. In dsPICs, the user can decide whether to wait for the next PWM period to update this new duty value, or to change it immediately. The choice is up to the designer.

Digital Center-Aligned PWM Generator

Let us now review a different technique that can be selected within the PWM peripheral to generate the output signal. It is called center-aligned PWM. The process is similar to the previous one in that an internal counter starts counting up from zero. The figure below demonstrates the concept. The clock is derived from the system clock, and the dashed line represents the counter content increasing from zero to some final value. At this point, nothing happens yet to the PWM output pin.


A DUTY CYCLE register is still used to hold a number that represents the active high duration time. A second comparator continuously checks the DUTY CYCLE register and the counter contents. If they match:

  • while the counter is counting up, the output PWM pin is set.
  • while the counter is counting down, the output PWM pin is reset.

In the figure below, we can see that the output signal becomes symmetric with respect to the point when the counter has reached its max value and starts counting down. As already stated in the previous section, the PWM period and the active high duration are functions of the clock used by the PWM peripherals. The equations are similar to those already shown for the edge-aligned mode and hold true for the period and duty cycle calculation.


As for the edge-aligned signal, any duty cycle can be chosen. Once again, there may be some limitations due to hardware implementation on very small and very large duty values.


16-bit Clocking Scheme
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