Buck Converter

Buck Converter Basics

The basic buck-converter-block diagram is shown below. We have the DC input voltage (Vdc) and a switch that periodically, at frequency fpwm, opens and closes the path to the right side. The relative ratio of the output high- and low-time intervals generates different output voltages. The output power is modulated, thus, changing the duty cycle of the signal that turns on and off the switch.


Because of the switch, the voltage V1 is a square wave. Its duty cycle varies to control the output voltage. Using Fourier expansion, we can express the periodic square wave as a DC value, the function of the amplitude of the square (A) wave times the ratio between its active time interval and the period (T), adding it to the sine waves at increasing (multiple) frequencies.


The output L1, C1 filter is needed to extract the DC term, eliminating all the frequency dependent components. The design of this low-pass filter must present a high attenuation at the PWM frequency, which is generally not an issue since the trend in the design of converters is to have this frequency to be as high as possible. The output of the low pass filter is the average voltage Vave. There are also additional design constraints in the selection of L1 and C1 we will address this topic in the next few pages.


Let's examine the behavior of the circuit during the first two time intervals: when the switch Q1 is closed and when it is open. As shown below in the signal driving the switch Q1 is a square wave with variable duty cycle. This waveform is normally generated by the PWM peripheral of the SMPS dsPIC® DSC. The sum of Ton and Toff makes the full switching period T.


In the following analysis of the circuit, it's assumed that the system is already at steady state, i.e., all transients in the system have died down and the output voltage has already reached its final, nominal value. This approach is useful to understand the general behavior of the circuit. A more precise analysis and comprehensive of transients can be carried out with simulation software if needed.

During Ton, the circuit can be redrawn as shown below. The diode is reverse-biased so that it is not conducting. The left side of the inductor is more positive than the right side and the voltage on it can be easily computed. Be mindful that we assume we're in the steady state, so that the output voltage is, Vo, and the the inductor voltage as indicated by the equation. VQ on is the voltage drop across the switch when it is closed. This term can be often neglected, since it is much smaller that the other values. Some energy is stored in the magnetic field of the inductor. The current, from the input source, flows at the output splits between the load resistor RL and the cap, C1 charging it.


The current flowing into the inductor is related to the inductor voltage by this equation below. It is easy to see that the inductor current has a linear behavior with positive slope.


Below we've grouped the relevant equations describing the circuit during Ton.


During Toff, the circuit is as shown below. Switch Q1 is open. The inductor will try to keep the current flow in the same direction; but this means that the voltage on the inductor itself will reverse polarity. Now the right side is more positive than the left side. Node V1 will try to become negative, but the diode D1 will prevent it from going lower than 0.7V below ground (this is the freewheeling function of the diode's forward bias voltage). We can think of the inductor as operating, during Toff, as a generator supplying the current to the load resistor. The cap, C1, will also contribute to keeping the output voltage constant. The voltage on the inductor becomes as indicated in the equation.


The current, during Toff, still has a linear (down slope) behavior since the voltage on the inductor is constant and negative as shown in the diagram below.


Here we see the equations that describe the circuit behavior during Toff. VD on is the forward voltage drop on the diode D1.


Ripple Current

Let's look at the current flowing through the inductor during each period T. As described previously, we will take advantage of operating the system at steady state. In this condition, the current flowing into the inductor at the end of each PWM period must be equal to the current at the beginning of the (following) period. If this is not true, it means that the system has not reached the steady state condition yet, or some kind of perturbation has occurred. The steady state condition is then easy to compute including the current ripple value. Note that the inductor current is also the output current if we consider the output capacitor to be ideal, so that all the ripple current flows into ground. The average value of the inductor output current is then computed as the sum of the current at the beginning of the period and one-half the ripple value.


Input-Output Relationship

As we have seen previously, the linear (up- or down-slope) behavior of the inductor current is the result of a constant (respectively, positive and negative) inductor voltage, as shown in the upper plot below. We can equate the current increased value during Ton to the current decrease value during Toff. Note that steady state they must be equal, as we have seen in the previous diagram. Neglecting for the diode and the switch forward voltages for simplicity, we get a linear relationship between input and output. The proportionality constant is the duty cycle, that is the ratio Ton/T.

As you can see from the plot, the requirement for the initial and final inductor current to be equal reverts to the fact that the two shaded areas in the middle graph must equal to each other, i.e., A1 = A2.


Duty Cycle Limit

From the input-output relationship above, it's easy to see that, once the output voltage has been defined, the maximum duty cycle in the system will be reached when the input voltage is at its minimum. The corresponding equation allows us to determine which will be the maximum duty cycle once the input voltage range and the output fixed voltage are specified.


Buck Converter Modes

A buck converter can be operated in the various modes listed below and is described in the next few sections.

Continuous Mode

Typically, a buck converter is designed to work only in continuous mode. This will make the control loop easier to implement and control. However, at very low load (or even no load at all), the system can operate in critical or even discontinuous mode.

For continuous mode, the inductor current is always greater than zero. In other words, Imin > 0 at any time.
One of the great advantages of the continuous mode is that the relationship between output and input voltages is linear.


Critical Mode

The converter is operating at critical mode when, at the beginning and the end of each PWM period, the inductor current reaches zero. The inductor average current value in this mode is called limit current and equals one-half of the peak current. See diagram below.


Discontinuous Mode

The converter is operating in discontinuous mode if the inductor current reaches zero before the end of the PWM period. This means that the output current Io, ave is lower than the Io, limit current previously described.


A buck converter – voltage mode – can be implemented using a dsPIC. Apart from the power circuits, everything is inside the dsPIC. The required peripherals are:

  • One ADC channel
  • One (complimentary, if synchronous buck) PWM channel

For more details, please visit Digital Power Converter Basics using dsPIC33 Digital Signal Controllers

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