The diagram below presents the third possible control loop system, Average Current Mode (ACM), and how it may be operated in an analog implementation. Average current mode loop is quite similar to peak current mode architecture in that there are two loops:
- Outer loop: This is the voltage control loop where the comparison of the output voltage with the reference voltage provides the error; this is processed by the voltage compensator (green box). Its output is the reference current.
- Inner loop: This loop measures the average current flowing into the inductor and compares it to to the reference current. The current error is then processed by the current compensator (pink box) to generate a signal that is compared with the locally generated sawtooth signal. The comparator output drives through the two usual flip-flops that control the switches.
A simplified explanation of the differences between average and peak current mode loops is provided below.
In the specific case of the buck converter (note that similar reasoning holds for other topologies) the current flowing into the inductor is also the current flowing to the output. However the inductor current has a quite wide ripple, due to the ramp up and ramp down of the current itself. The inductor current thus has two contributions:
- An average value
- A superimposed ripple
The output cap is seen as a short circuit to ground by the ripple component of the current. In an ideal condition the ripple current will completely and exclusively flow to ground through the cap. This means that the output current will be the inductor average current. It should be clear at this point the importance of ACM control, since it directly controls the average current. PCM control, under certain conditions, is equivalent to ACM control. This is true when, in each PWM period, the inductor current does not go to zero. Note that controlling the peak of the current has the same effect as controlling the average current.
A final note: in an analog implementation, the SAW generator, the comparator (or the summing node) and the flip–flop (including associated control circuitry) are generally embedded in a single chip, typically referred to as the PWM generator. These chips often embed the MOSFET drivers. The compensators are normally designed using op amp and passive components.
The following shows how a buck converter in average current mode can be implemented using dsPIC. Apart from the power circuits, everything is inside the dsPIC. The required resources are:
- One ADC channel for the output voltage measurement
- One ADC channel for the inductor current measurement
- One (complimentary, if synchronous buck) PWM channel
The error is generated by comparing the real output voltage and the reference voltage. This voltage is processed by the PID. The output of this PID processing is the reference current and it is compared with the current value that is read by the ADC. The current error is processed by the second PID controller and the output value is the duty cycle value.
Multi-Phase architectures are mainly used when:
- Required output current is high
- The designer wants to reduce the current ripple.
- Traditional buck architecture is doubled and the two outputs are connected together. The two PWM signals are then generated with a 180° phase shift.
The diagram below shows the two waveforms that represent the currents into the two inductors. They are 180° of out-of-phase.
As a result, the total output current is the sum of the two inductor currents. We can see that the current ripple is at double the frequency of the PWM signal (higher frequency ripple is easier to filter out because a smaller L and C are required) and the ripple amplitude is smaller compared to each single ripple.
A Muilti-phase converter in average current mode can also be implemented using a dsPIC. Apart from the power circuits, everything is inside the dsPIC. The required resources are:
- One ADC channel for the output voltage measurement
- One ADC channel for the first inductor current measurement
- One ADC channel for the second inductor current measurement
- One (complimentary, if synchronous buck) PWM channel for Buck 1
- One (complimentary, if synchronous buck) PWM channel for Buck 2
The error voltage generated by comparing the real output voltage and the reference voltage (the voltage we want to get at the output) is processed by the voltage PID. The output of this PID processing is the reference current. Since we have two branches in our converter, the total current is divided by two. This value is compared with the current values flowing in each branch, read by the ADC. The two current errors are processed by the current PID controllers and the output value is the duty cycle value for each PWM signal.
In the multi-phase converter, we have two ADC interrupt routines, one for each current reading. As for the first ADC ISR, the output of the first PID computation (voltage PID) is now the current reference.
Using the saved reference current value, the current error is calculated and used in the PID algorithm. The output of the PID is the new value of the Duty Cycle and is checked against the valid duty cycle range.
In the second ISR (Buck 2), the same reference current, calculated in ISR1, is compared to the Buck 2 current and the difference is the input of the PID. The output is the new value of duty cycle of Buck 2.