Buck Converter Peak Current Mode

The block diagram below shows the the analog implementation of a peak current mode control. The system consists of a combination of an outer voltage loop and an inner current loop.

The voltage loop is exactly the same we have seen in a previous sections: the output voltage is sampled and subtracted from the reference voltage, i.e., the voltage that we would like to obtain. The result of such a subtraction is the error in output voltage. It is processed by the voltage compensator (the block in the green box). The output of this compensator (current reference) is compared with the actual current flowing into the inductor. Some additional correction may be added (slope compensation), which may be required in some applications to make sure the system is stable. The comparison is done with a comparator, followed by the same flip-flip architecture to generate the complimentary signals required to drive the two MOSFETs of the system.


The advantage of using such a control approach compared to the voltage mode stems from the fact that (peak) current mode allows faster response of the system changes.

Digital Implementation
The diagram below shows how a buck converter using peak current mode can be implemented using a dsPIC®. Apart from the power circuits, everything is inside the dsPIC.

The required resources are:

  • One analog-to-digital converter (ADC) channel
  • One digital-to-analog converter(DAC) channel
  • One comparator
  • One (complimentary, synchronous buck) pulse width modulation (PWM) channel

Control Strategy
The error generated by the comparison of the real output voltage and the reference voltage (the voltage we want to get at the output) is processed by the voltage Proportional, Integral and Derivative (PID). The output of this PID processing is the reference value of the peak current that must be compared with the real peak current from the haredware. The output of the comparator switches off the active portion of the PWM period.


The comparator threshold is the number generated by the voltage PID processing. See diagram below.


The overall code architecture is the same as for the voltage mode. The only substantial differences are in the ADC interrupt service routine. Essentially, the PID computation output is now the comparator threshold voltage and must consequently be stored into the comparator DAC register as shown in the accompanying diagram.


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