dsPIC® DSCs Implementation Operations
PID term computation continued…
Moves the content of the RAM location pointed by W8 into register W4
Moves the content of the RAM location pointed by W10 into register W5
Updates the W10 register, so that it is now pointing to the previous RAM location
Store Accumulator Instruction
The diagram below shows the operation of the store accumulator instruction, sac.r.
We store the high part (from 16th to 31th bit) of the accumulator into the W0 register. Before saving it, the value is shifted 8 bit positions to the left and the resultant value is rounded. See diagram below.
Copy the content of register W5 [that is e(n-1)] into the last location of the error buffer.
The content of RAM location pointed by [W10 -4] is then copied into the W5 register.
The pointer W10 is decremented, to point to the previous location of the error buffer
The content of register W5 (that is the current errer e(n)) is stored into the RAM location pointed by W10. The purpose of the operations performed in the last few diagrams is to make room for the next value of the error that will arrive in the next sampling period.
The number of cycles required to perform the PID operations as indicated in the previous diagrams can be explained using the following example:
If the dsPIC® DSC is running at 40 MIPS, each machine cycle equals: 1/40 MHz = 25 ns. As a consequence, the total time required to perform the described task is 13 x 25 ns = 325 ns.