dsPIC® DSC SMPS Module Application

dsPIC33F SMPS Module Application

This module provides means for the SMPS dsPIC® Digital Signal Controller (DSC) devices to monitor voltage and current in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC® DSC processor and/or peripherals, without requiring the processor and analog-to-digital converter (ADC) to constantly monitor voltages or currents, frees the dsPIC® DSC to perform other tasks. The comparator module has a high-speed comparator and an associated 10-bit digital-to-analog Converter (DAC) that provides a programmable reference voltage to the inverting input of the comparator. The polarity of the comparator output is user-programmable. The output of the module can be used in the following modes:

  • Generate an interrupt
  • Trigger an ADC sample and convert process
  • Truncate the PWM signal (current limit)
  • Truncate the PWM period (current minimum)
  • Disable the PWM outputs (fault latch)

The output of the comparator module may be used in multiple modes at the same time, such as:

1) Generate an interrupt
2) Initiate an ADC sample and conversion
3) Truncate the PWM output in response to a voltage being detected beyond its expected value.

The comparator module can also be used to wake up the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold voltage.


The range of the DAC is controlled through an analog multiplexer that selects either AVDD/2, an internal reference source, Internal Reference (INTREF), or an external reference source, (EXTREF). The full range of the DAC (AVDD/2) will typically be used when the chosen input source pin is shared with the ADC. The reduced range option (INTREF) will likely be used when monitoring current levels using a current sense resistor. Usually, the measured voltages in such applications are small (<1.25V); therefore the option of using a reduced reference range for the comparator extends the available DAC resolution in these applications. The use of an external reference enables the user to connect to a reference that better suits their application. DACOUT, shown in figure below, can only be associated with a single comparator at a given time.


dsPIC33F SMPS: Interaction with I/O Buffers

If the comparator module is enabled and a pin has been selected as the source for the comparator, then the chosen I/O pin must disable the digital input buffer associated with the pin to prevent excessive currents in the digital buffer due to analog input voltages.

dsPIC33F SMPS: Digital Logic

The CMPCONx register, see figure below, provides the control logic that configures the comparator module. The digital logic provides a glitch filter for the comparator output to mask transient signals in less than two instruction cycles. In Sleep or Idle mode, the glitch filter is bypassed to enable an asynchronous path from the comparator to the interrupt controller. This asynchronous path can be used to wake-up the processor from Sleep or Idle mode. The comparator can be disabled while in Idle mode if the CMPSIDL bit is set. If a device has multiple comparators, if any CMPSIDL bit is set, then the entire group of comparators will be disabled while in Idle mode. This behavior reduces complexity in the design of the clock control logic for this module. The digital logic also provides a one TCY width pulse generator for triggering the ADC and generating interrupt requests. The CMPDACx register provides the digital input value to the reference DAC. If the module is disabled, the DAC and comparator are disabled to reduce power consumption.


The comparator module is controlled by the following registers:

  • CMPCONx: Comparator Control x Register
  • CMPDACx: Comparator DAC x Control Register

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