NOTE: Microchip updates its tools regularly. This page is an older version that we have preserved for the convenience of those who are supporting existing designs based upon older versions of our tools. Please check www.microchip.com/developerhelp for the updated version of this page.
JTAG is the common name used for a debugging, programming, and testing interface typically found on microcontrollers, ASICs, and FPGAs. It enables all components with this interface to be tested, programmed, and/or debugged using a single connector on a PC board which can daisy chain them together.
JTAG (Joint Test Action Group) is the name of the group that defined the IEEE 1149.1 standard. This standard defines the TAP (Test Access Port) controller logic used in processors with JTAG interfaces.
For detailed information, please see this wikipedia JTAG entry.
Typical JTAG System and Pin Definitions
A full JTAG interface requires five pins. In many systems, the optional TRST pin is not implemented, resulting in a FOUR wire interface.
| Pin Name | JTAG Pin Description |
|---|---|
| TMS | Test Mode Select |
| TCK | Test Clock Input |
| TDI | Test Data Input |
| TDO | Test Data Output |
| TRST | Test Reset (optional) |
Typical Implementation
The figure below illustrates how a typical JTAG system could be configured:
- TMS - selects the device under test
- TCK - clocks data into TDI
- TDI - the test or programming data input, cascaded through all JTAG compliant devices in the system
- TDO - the resulting output
JTAG Connector
There is no standard JTAG connector or pinout, so suppliers are able to define their own. Microchip uses the pin arrangement illustrated below on those development boards, such as the Explorer 16 Development Board, that are JTAG enabled. Note that most PIC32 starter kits are NOT JTAG enabled because they contain an on-board equivalent of the PICkit.
