Example Application using the PTG

Interleaved Sampling Intervals for ADC conversions

Figure XI-1 shows the waveform for an application which, after being triggered by a PWM period, acquires 25 consecutive Analog-to-Digital Converter (ADC) samples of a signal modified by the PWM pulse. This sampling process is repeated over a number of PWM periods. To help ensure validity of the data, the application does not begin the sampling at the same time interval after each PWM cycle. The start time of the sampling alternates between five and six microseconds on each PWM cycle.


  1. Each cycle of the programmed PTG sequence initiates a trigger generated by the PWM peripheral. (A PTG IRQ will also be initiated upon the PWM trigger to inform the application of the status of the sequence.)
  2. After receiving the PWM trigger, the PTG waits a number of cycles determined by PTGTOLIM before beginning the 25 ADC conversions. PTGT0LIM is initialized to provide a five-microsecond delay on the first pass of the PTG sequence.
  3. A trigger signal is sent to the ADC initiating a conversion. After sending out the ADC trigger, the PTG pauses to allow the conversion to be completed. The length of the pause is determined by the value of PTGT1LIM.
  4. Step 3 is repeated 24 times.
  5. After 25 conversions, PTGT0LIM is adjusted to provide a six-microsecond pause after the next PWM trigger. Program control is transferred to Step 1, allowing the next PWM trigger to generate 25 samples after a six-microsecond pause.
  6. After the second set of 25 conversions have been completed, the delay time is reset to the original five-microsecond delay. Control is then transferred back to Step 1 to begin repeating the sequence.

This dual-loop sequence repeats until the application program causes the PWM peripheral to stop sending triggers to the PTG. The IRQ generated in Step 1 can be used to provide the application the necessary information on the status of the PTG sequence.

Flow Chart

Example Code

Initalizing the PTG Registers

Initialization Considerations: The initial values placed in the ADJ, HOLD, and LIM registers are based upon the speed of the PTG clock. This example presumes that there are 14 PTG clocks each microsecond. This example also presumes that 11 PTG clocks provide a sufficient amount of time for an ADC conversion to complete. Please verify the times for the MCU you are using.

Step Commnads

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