High-Speed Devices begin the enumeration process as Full-Speed Devices. During the reset phase High-Speed Devices and High-Speed Capable Hubs begin a negotiation process to determine if they can mutually move into high-speed mode. This process starts by asserting a voltage on D+ and D-, and is shown in detail in the following diagram:
During reset a High-Speed Device will assert a 17.8 mA signal on D- for at least 1 ms. This causes the hub to see a voltage of 0.8 V on D-. If the hub is high speed capable it will respond. Low speed and full speed only hubs will ignore this signal.
Hub's K-J Chirp Response
Within 100 μs of detecting the device chirp, a High-Speed-Capable Hub will respond with a series of alternating K-J chirps. Each chirp is 50 μs long.
After three consecutive K-J chirps are detected, the device will connect a termination load on D+ and D-, allowing the system to conduct high speed communications. The hub will continue to send K-J chirps until just before the reset sequence is terminated.
End of Reset Sequence
When the reset sequence concludes the device and the port on the hub will be operating in high-speed mode.