16-bit PIC® MCU Data Memory

Simplified Diagram of a 16-bit PIC® Data Memory

PIC24 Microcontrollers (MCUs) and dsPIC® DSCs address 64 kBytes of data memory space. The amount of actual data memory available varies from device to device.

Only the lower 32 kBytes can be directly populated with RAM. No memory is physically provided in the upper 32 K address. Under program control, the upper 32 kBytes of address space can either point to a section of flash program memory or an extended data memory array.

Data Memory Regions

  • Special Function Registers (SFRs): The first 2 kBytes of memory in 16-bit MCU and DSCs contain the SFRs for the device. SFRs are used primarily to access the MCU peripherals.
  • Data Memory: Data RAM begins at address 0x800.
  • Direct Memory Access (DMA): For devices with DMA, a dedicated block of dual-port memory is located in the data space immediately following the last byte of installed data RAM. This DMA buffer is used to hold information being sent to or received from peripherals through the DMA controller. Not all devices offer DMA and for those that do, the size of this buffer can vary. Please refer to the device's datasheet for specifications.
  • Unimplemented Memory: The 32 kByte data space located at address 0x8000-0xFFFF can be used to access either Flash program memory or to access an additional block of data memory. No physical memory exists at these addresses. Details on accessing Flash through the data space can be found on this page: Program Space Visibility. Details on extending data memory can be found on this page: Extended Data Space.

Little-endian Data Alignment

Word data is aligned in the little-endian format: with the Least Significant Byte (LSB) at the even address (LSb = 0) and the Most Significant Byte (MSB) at the odd address (LSb = 1).

Near and Far Memory

PIC24 MCUs and dsPIC DSCs have 24-bit wide instructions. Several of these instructions have two modes in which to address an operand: Direct or Indirect.

  • Direct addressing uses 13 bits of the instruction to specify an operand's address. The effective range of direct addressing is from address 0 through address 0x1FFF (213).
  • Indirect addressing uses one of the 16-bit Working registers to hold the address of the operand. The destination address must be in the W register when the instruction is executed. The instruction specifies which W register contains the address of the operand. With indirect addressing, the entire 64 kBytes (216) can be accessed.

The memory which can be directly addressed is referred to as Near memory and memory which must be indirectly addressed as Far memory.

The default setting for the MPLAB® XC16 compiler is to begin placing data variables that are always accessed indirectly (i.e. arrays, strings, and structures) into far memory and all directly accessed variables into near memory. This setting is considered the optimum for most applications as no pre-loading instructions are inserted by the compiler into the application code. Programmers do not typically concern themselves with the location of variables until the number of variables becomes too large to fit in near memory.

As an application grows and fills up near memory, the performance of the application's control loops may change. Developers may wish to direct the compiler as to an area where a particular variable is to be placed. See the "MPLAB XC16 User's Manual" for more details.

dsPIC X and Y Memory

dsPIC DSCs add 19 Digital Signal Processor (DSP) instructions to the PIC24 architecture. To implement typical DSP algorithms, sequential DSP instructions need to be executed with two new data values loaded into each instruction cycle. To pipeline this data flow and allow two operands to be brought into the CPU for each instruction, the DSC splits the data memory into two sections. This only occurs when the DSC executes a DSP class of instructions. When split, ON operands for each DSP instruction can be simultaneously accessed on BOTH buses.

For MCU instructions (i.e., instructions that are NOT classified as DSP instructions) the data memory is identical to the PIC24 MCU data memory.

Simplified Block Diagram of a dsPIC® Digital Signal Controller (DSC) when Executing a Digital Signal Processor (DSP) Instruction

When a dsPIC DSC executes a DSP instruction:

  • Data memory appears to consist of two regions: X and Y.
  • Two data buses are available to concurrently access data memory. One bus accesses the X memory space and the other is dedicated to accessing the Y memory.
  • Simultaneous read/modify/write-backs may be executed on both data buses.

 Learn More

16-Bit Peripherals
Extending Data Memory
Reading Flash Memory (PSV)
Direct Memory Access

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.