Establishing Step Command Timing

When setting up the clock controlling the execution speed of the Peripheral Trigger Generator (PTG) Step Commands, three parameters need to be considered:

1. The signal used as the base clock source for the PTG Module.
2. The number of clock periods needed for each Step Command cycle (prescaler).
3. Whether or not the sequence will need to extend the clock cycle (step delay timer).

Clock Source and Prescaler

The PTG Control Register (PTGCON) controls the clock source and the prescale value for the PTG module. There are six signals which can be set as the PTG clock. Once the clock has been determined, the application can divide the clock by a value between 1 and 32.

Selecting the PTG clock and prescaler using the MPLAB^® XC16 C Compiler

Delaying PTG Step cycle.

Using the PTG Step Delay Limit register (PTGSDLIM) causes the Step Commands lot to execute at a slower rate than the period set by PTGCON. When enabled, PTGSDLIM acts as a second prescaler for the PTG Module. The PTG clock will be divided by the value of PTGSDLIM. The use of the step delay timer is optional, as it can be enabled or disabled at runtime by using the PTGCTRL Step Command.

• PTGCTRL with <OPTION> = 0b0010 (2) Disables the Step Delay.
• PTGCTRL with <OPTION> = 0b0110 (6) Enables the Step Delay.

 Learn More

• Programming the PTG
• Initializing the PTG
• Starting and Stoping the PTG at Runtime
• Example PTG Code