Cortex® M0+ AHB-APB Bridge

The AMBA High-performance Bus and Advanced Peripheral Bus(AHB-APB) bridges enable a Arm® Cortex®-M0+ CPU to seamlessly access peripherals. AHB-APB bridges are slaves on the AHB bus synchronizing the time domains of the high-speed AHB bus with the lower speed clocks used by the peripherals. Read/write authentication functions between the CPU and peripheral register are performed by the AHB-APB bridges.


Peripheral Architecture

Peripheral access registers on a Cortex-M0+ MCU are mapped to memory addresses. The address for a peripheral is determined by the bus the peripheral is attached to. For example, SAMD21 MCUs have three memory busses accessed through three bridges.


Peripheral Clocking

Each peripheral on an M0+ MCU can have up to three clocks.

See the datasheet of the device you are using to see which clocks are needed for each peripheral.

  • AHB Clock CLK_AHB - generated by the Power Manager, this clock is identical in phase and frequency to the CPU's clock. Peripherals use this clock to ensure they are synchronized with the CPU. To reduce power consumption, the Power Manager has the ability to distribute the AHB clock to only a set of peripherals you selected.
  • Peripheral Bus Clock CLK_xxxx_APB - also generated by the Power Monitor, are synchronous to the AHB clock, but are typically divided down to a lower frequency. Peripheral bus clocks are used by peripherals such a Timer Counters (TC) and Timer Counters for Control (TCC.) As with the AHB clock, the Power Manager has the ability to select the peripherals who receive the bus clock.
  • Generic Peripheral Clocks GCLK_PERIPHERAL - generated by the Generic Clock Controller (GCLK) and may be asynchronous to the CPU clock. There can be up to eight peripheral clocks on each device. Peripherals which need a Peripheral Clock include the communication peripherals such as the SERCOM. The General Clock controller generates the peripheral clock(s) and distributes them to user-selected peripherals.

Configuration and Initialization

As an architectural feature of Cortex-M0+ MCUs, the AHB-APB bridges require no user-written initialization code. Microchip has assigned each peripheral to a bus and specified the individual memory addresses for each of the peripheral registers. You cannot alter the factory defined configuration.

Before the CPU can access peripherals through AHB-APB bridge, the following steps must be taken.

  • The Power Manager must be configured to:
    • generate the AHB clock CLK_AHB,
    • generate the clocks for each bus on the MCU CLK_APBA, CLK_APBB, …etc.,
    • and distribute the bus clock(s) to the user-selected peripherals.
  • The Generic Clock Controller must generate and distribute any Peripheral Clocks needed by the application.

 Learn More

Power Manager (PM)
Learn more >
Configuring the Power Manager
Learn more >
Generic Clock Controller (GCLK)
Learn more >
Configuring GCLK
Learn more >
© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.