Module Overview
The System Controller (SYSCTRL) provides a user interface to the clock sources, brownout detectors, on-chip voltage regulator and voltage reference of the device. It is the central control for the SAM device. Through its interface registers, it is possible to enable, disable, calibrate, and monitor all the SYSCTRL sub-peripherals shown in the block diagram.
System driver
The System driver provides an interface for the configuration and management of the device's system relation functionality (such as clocks, reset cause determination, etc.) that is required for all applications. This is not limited to a single peripheral but extends across multiple hardware peripherals. It contains several sub-modules that control one specific aspect of the device.
The following peripherals are used by the System driver:
- System Control (SYSCTRL)
- Power Manager (PM)
- System Core
- System Clock Control
- System Interrupt Control
- System Pin Multiplexer Control
Voltage References
The various analog modules within the SAM devices (such as AC, ADC, and DAC) require a voltage reference to be configured to act as a reference point for comparisons and conversions. The SAM devices contain multiple references, including an internal temperature sensor and a fixed bandgap voltage source. When enabled, the associated voltage reference can be selected within the desired peripheral where applicable.
System Reset Cause
In some applications, there may be a need to execute a different program flow based on how the device was reset. For example, if the cause of reset was the Watchdog timer (WDT), this might indicate an error in the application, and a form of error handling or error logging might be needed.
For this reason, an API is provided to retrieve the cause of the last system reset, so that appropriate action can be taken.
Sleep Modes
SAM devices have several sleep modes. The sleep mode controls which clock systems on the device remains enabled or disabled when the device enters a low power sleep mode. The table below lists the clock settings of the different sleep modes.
| Sleep | CPU clock | AHB clock | APB clocks | Clock sources | System clock | 32 KHz | Reg mode | RAM mod |
|---|---|---|---|---|---|---|---|---|
| Idle 0 | Stop | Run | Run | Run | Run | Run | Normal | Normal |
| Idle 1 | Stop | Stop | Run | Run | Run | Run | Normal | Normal |
| Idle 2 | Stop | Stop | Stop | Run | Run | Run | Normal | Normal |
| Standby | Stop | Stop | Stop | Stop | Stop | Stop | Low Power | Source/Drain biasing |
Before entering device sleep, one of the available sleep modes must be set. The device automatically wakes up in response to an interrupt being generated or upon any other sleep mode exit condition.
Some peripheral clocks remain enabled during sleep, depending on their configuration. If desired, the modules can remain clocked during sleep to allow them to continue to operate while other parts of the system are powered down to save power.