SAM L10/L11 Configurable Custom Logic (CCL)

Configurable Custom Logic (CCL)


The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device pins, to events, or to other internal peripherals. This allows you to eliminate logic gates for simple glue logic functions on the Printed Circuit Board (PCB). Each LookUp Table (LUT) consists of three inputs, a truth table, an optional synchronizer/filter, and an optional edge detector. Each LUT can generate an output as a user-programmable logic expression with three inputs. Inputs can be individually masked. The output can be combinatorially generated from the inputs and can be filtered to remove spikes. Optional sequential logic can be used. The inputs of the sequential module are individually controlled by two independent, adjacent LUT (LUT0/LUT1) outputs, which enables a complex waveform generation.


  • Glue logic for general purpose PCB design
  • Up to two programmable LUTs
  • Combinatorial logic functions: AND, NAND, OR, NOR, XOR, XNOR, NOT
  • Sequential logic functions: Gated D Flip-Flop, JK Flip-Flop, Gated D Latch, RS Latch
  • Flexible LUT inputs selection:
    • I/Os
    • Events
    • Internal peripherals
    • Subsequent LUT output
  • Output can be connected to the I/O pins or the Event System
  • Optional synchronizer, filter, or edge detector available on each LUT output

Block Diagram


Principle of Operation

The CCL can take inputs and generate output through I/O pins. For this to function properly, the I/O pins must be configured to be used by a LUT.

The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the Main Clock module, MCLK (see MCLK - Main Clock), and the default state of CLK_CCL_APB can be found in Peripheral Clock Masking. A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using input events, filter, edge detection, or sequential logic. GCLK_CCL is required when input events, a filter, an edge detector, or a sequential submodule is enabled. Refer to GCLK - Generic Clock Controller for details.
This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).

The CCL can use events from other peripherals and generate events that can be used by other peripherals. For this feature to function, the events have to be configured properly. Refer to the Related Links below for more information about the Event Users and Event Generators.

The CCL can serve as glue logic between the device and external devices. The CCL can eliminate the need for external logic components and can also help the designer overcome challenging real-time constraints by combining core independent peripherals in clever ways to handle the most time-critical parts of the application independent of the CPU.

Refer to the "CCL – Configurable Custom Logic" chapter from the product data sheet for more details.

Code Example

This CCL application note describes various features of the CCL peripherals and is supplied with an IR encoding example application which is applicable for the SAM L10/L11 family.

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