Embedded Flash Description

SAM L10/L11 devices embed 16 kB, 32 kB or 64 kB of internal Flash mapped at address 0x00000000. The Flash has a 512-byte (64 lines of 8 bytes) direct-mapped cache which is disabled by default after power-up. The Flash is organized into rows, where each row contains four pages. The Flash has a row-erase and a page-write granularity. The Flash is divided into different regions. Each region has a dedicated lock bit preventing writing and erasing pages on it.

Cache

The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. Only the Flash area is cached (Data Flash is not). It is a direct-mapped cache that implements 64 lines of 64 bits (that is, 512 bytes). The NVM Controller cache can be enabled by writing "0" to the Cache Disable bit in the Control B register (CTRLB.CACHEDIS). The cache can be configured to three different modes using the Read Mode bit group in the Control B register (CTRLB.READMODE). The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines (CTRLA.CMD = INVALL). Commands affecting NVM content automatically invalidate cache lines.

Related Peripherals

The related peripheral to control the Embedded Flash is the NVM Controller (NVMCTRL).

Embedded Flash Architecture

The Flash panel is composed of three sections:

• The Main Flash Array
• The Data Flash
• The Calibration & Auxiliary Space (NVM Rows)

Main Flash Array Charcteristics:

• Up to 64 kB of Flash Memory (NVM main array)
• Organized into 256-byte rows
  • One row = Four 64-byte pages
• 512 bytes of direct-mapped cache
• 16 Region Lock bits
• Endurance: 100 K Cycles (typical)
• Support Secure/Non-Secure regions' configuration for Arm® TrustZone® technology (SAM L11 only)
• Speed Characteristics
  • 0 WS @ 6MHz / 1 WS @ 8MHz (Performance Level PL0)
  • 0 WS @ 14MHz / 2 WS @ 32MHz (Performance Level PL2)

References