SAM L10/L11 Main Clock (MCLK) Controller

Main Clock (MCLK) Controller


The MCLK controls the synchronous clock generation of the device. Using a clock provided by the Generic Clock Module (GCLK_MAIN) or the DFLLULP (CLK_DFLLULP), the MCLK Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling you to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance or vice versa. In addition, the clock can be masked for individual modules, enabling you to minimize power consumption.

The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only be re-enabled by a reset. The Generic Clock GCLK_MAIN or the DFLLULP Clock CLK_DFLLULP is required to generate the Main Clocks. GCLK_MAIN is configured in the Generic Clock Controller (GCLK), and can be re-configured if needed. CLK_DFLLULP is configured in the Oscillators Controller (OSCCTRL).

By default the MCLK clock source is supplied by the Generic Clock Generator 0 (GCLK0).

Refer to the MCLK – Main Clock Controller chapter from the product data sheet for more details.

Block Diagram


Code Example

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