SAM L10/L11 Power Manager (PM)

Power Manager (PM)

Overview

The PM controls the Sleep modes and the power domain gating of the device.

Various Sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. While in active mode, the CPU is executing application code. When the device enters a Sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the Sleep mode. The application code decides which Sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a Sleep mode to Active mode.

The Performance Level (PLx) technique consists of adjusting the regulator output voltage to reduce power consumption. You can select on the fly the performance level configuration which best suits the application.

The power domain gating technique enables the PM to turn off unused power domain supplies individually while keeping others powered up. Based on activity monitoring, power domain gating is managed automatically by hardware without software intervention. This technique is transparent for the application while minimizing static consumption. You can also manually control which power domains will be turned on and off in standby Sleep mode.

The internal state of the logic is retained (retention state) allowing the application context to be kept in non-active states.

Features

  • Power management control
    • Sleep modes: Idle, Standby, and Off
    • Performance levels: PL0 and PL2
    • SleepWalking available in Standby mode.
    • Full retention state in Standby mode
  • Power Domain Control
    • Standby Sleep mode with static power gating
    • SleepWalking extension to power gating
    • SRAM sub-blocks retention in Standby mode

Block Diagram

saml10-power-manager.png

Principle of Operation

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it can only be re-enabled by a system reset.

The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt controller to be configured first.

When the CPU is halted in debug mode, the PM continues normal operation. If standby Sleep mode is requested by the system while in debug mode, the power domains are not turned off. As a consequence, power measurements while in debug mode are not relevant.

If off, sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the off mode upon a reset condition, the core domains are reset except the debug logic, allowing you to keep using their current debug session.

Hot plugging in Standby mode is supported except if the Switchable Power Domain (PDSW) is in retention state. Cold plugging in off mode is supported as long as the reset duration is superior to (Tmin).

Registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC Write-Protection is not available for the Interrupt Flag (INTFLAG) register. Optional PAC Write-Protection is denoted by the PAC Write-Protection property in each individual register description. Write-protection does not apply to accesses through an external debugger.

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Refer to the "PM – Power Manager" chapter from the product data sheet to get more details.

Code example

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