SAM L10 Processor Overview

Cortex®-M23 processor

The SAM L10 implements the Arm® Cortex®-M23 processor, based on the Arm®v8-M architecture. It is the smallest and the most energy-efficient Arm processor with Arm® TrustZone® technology.

As of July 2019, the implemented Arm Cortex-M23 is revision "r1p0."

The Arm Cortex-M23 core has two bus interfaces:

  • Single 32-bit Arm® AMBA® 5 AHB Protocol - Lite system interface that provides connections to peripherals and memories.
  • Single 32-bit I/O port bus interfacing to the PORT and Crypto Accelerator peripherals with 1-cycle load and store.

For more information, refer to the following documents available from Arm:
"White Paper: Cortex-M for Beginners - An overview of the Arm Cortex-M processor family and comparison"
"Arm® v8-M Architecture Reference Manual"
"Arm® Cortex®-M23 Devices Generic User Guide"
"ARM® Cortex®-M23 Processor Technical Reference Manual"

Cortex-M23 Configuration

Table 1 shows the configurable options for the core and which options are enabled for the SAM L10 implementation:

Table 1


Cortex-M23 Core Peripherals

System Timer (SysTick)

The System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer to the "Arm® Cortex®-M23 Devices Generic User Guide" for details.

Nested Vectored Interrupt Controller (NVIC)

External Interrupt signals connect to the NVIC and the NVIC prioritizes the interrupts. The software can set the priority of each interrupt. The NVIC and the Cortex-M23 processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to the "ARM® Cortex®-M23 Processor Technical Reference Manual" as well as the "Arm® Cortex®-M23 Devices Generic User Guide" for details.

Single-Cycle I/O Port Bus (IOBUS)

The Cortex-M23 processor implements a dedicated, single-cycle I/O port bus for high-speed, single-cycle access to certain peripherals. The single-cycle I/O port bus is memory-mapped and supports all the load and store instructions. This bus is used on SAM L10 to provide single-cycle access to the PORT registers.

System Control Block (SCB)

The System Control Block provides system implementation information and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the "ARM® Cortex®-M23 Processor Technical Reference Manual" for details.

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