Serial Communication Interface (SERCOM)

Overview

There are up to three instances of the SERCOM peripheral. A SERCOM can be configured to support a number of modes: I²C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.

The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to be operated in all Sleep modes.

Features

• Interface for configuring into one of the following:
  • Inter-Integrated Circuit (I²C) Two-wire Serial Interface
  • System Management Bus (SMBus™) compatible
  • Serial Peripheral Interface (SPI)
  • Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
• Single transmit buffer and double receive buffer
• Baud-rate generator
• Address match/mask logic
• Operational in all Sleep modes with an external clock source
• Can be used with DMA

Block Diagram

Principle of Operation

Using the SERCOM I/O lines requires the I/O pins to be configured using the IO Pin Controller (PORT). The SERCOM has four internal pads, PAD[3:0], and the signals from I²C, SPI and USART are routed through these SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode-specific chapters for details.

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock.The SERCOM uses two generic clocks—GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW.

• The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a master.
• The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions.

These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM.

The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains.

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used. The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used.

The basic structure of the SERCOM serial engine is shown below:

The transmitter consists of a single write buffer and a shift register. The receiver consists of a one-level (I²C), two-level or four-level (USART, SPI) receive buffer and a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I²C operation.

The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE).