SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter (USART)

Overview

The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver.

The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The write buffer supports data transmission without any delay between frames. The receiver consists of a two-level or four-level receive buffer and a shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception.

Features

• Full-duplex operation
• Asynchronous (with clock reconstruction) or synchronous operation
• Internal or external clock source for asynchronous and synchronous operation
• Baud-rate generator
• Supports serial frames with five, six, seven, eight or nine data bits and one or two stop bits
• Odd or even parity generation and parity check
• Selectable LSB- or MSB-first data transfer
• Buffer overflow and frame error detection
• Noise filtering, including false start-bit detection and digital low-pass filter
• Collision detection
• Can operate in all sleep modes
• Operation at speeds up to half the system clock for internally generated clocks
• Operation at speeds up to the system clock for externally generated clocks
• RTS and CTS flow control
• IrDA modulation and demodulation up to 115.2 kbps
• LIN Slave support
• Auto-baud and break character detection
• ISO 7816 T=0 or T=1 protocols for Smart Card interfacing
• RS485 Support
• Start-of-frame detection
• Two- or Four-Level Receive Buffer
• Can work with DMA

Block Diagram

Principle of Operation

Using the SERCOM I/O lines requires the I/O pins to be configured using the IO Pin Controller (PORT). When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins. Both PORT control bits, PINCFGn.PULLEN and PINCFGn.DRVSTR, are still effective. If the receiver or transmitter is disabled, these pins can be used for other purposes.

The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals.

A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB), therefore, writing to certain registers will require synchronization to the clock domains.

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used. The interrupt request line is connected to the Nested Vectored Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used.

The USART uses the following lines for data transfer:

• RxD for receiving
• TxD for transmitting
• XCK for the transmission clock in synchronous operation

USART data transfer is frame-based. A serial frame consists of:

• One start bit
• From five to nine data bits (MSB or LSB first)
• No even or odd parity bit
• One or two stop bits

A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately, or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats. Brackets denote optional bits.

• St: Start bit. Signal is always low.
• n, [n]: Data bits. 0 to [5..9]
• [P]: Parity bit. Either odd or even.
• Sp, [Sp]: Stop bit. Signal is always high.
• IDLE: No frame is transferred on the communication line. Signal is always high in this state.