Reset Controller (RSTC)
Overview
Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the device to its initial state, and allows the reset source to be identified by the software. The RSTC collects the various reset sources and generates reset for the device. After a Power-On Reset (POR) event, the RSTC is enabled and the Reset Cause register (RCAUSE) indicates the POR source. The RSTC module is always enabled.
Features
- Resets the microcontroller and set it to an initial state according to the reset source.
- Resets the Cause register for reading the reset source from the application code.
- Multiple reset sources:
- Power supply reset sources: POR, Brown-out Detection (BOD12, BOD33).
- User reset sources: External Reset (RESET), Watchdog Reset, and System Reset Request.
RSTC Block Diagram
SAM L11 TrustZone Specific Register Access Protection
On SAM L11 devices, this peripheral has different access permissions depending on Peripheral Access Controller (PAC) Security Attribution (Secure or Non-Secure):
- If the peripheral is configured as Non-Secure in the PAC:
- Secure access and Non-Secure access are granted.
- If the peripheral is configured as Secure in the PAC:
- Secure access is granted.
- Non-Secure access is discarded (writes are ignored, reads return 0x0) and a PAC error is triggered.
Refer to "SAM L11 Peripheral Access Controller (PAC)" and the "Peripherals Security Attribution" paragraph from the product data sheet for more information.
Principle of Operation
The latest reset cause is available in the RCAUSE register and can be read during the application boot sequence in order to determine the proper action.
These are the groups of reset sources:
- Power Supply Reset: resets caused by an electrical issue; it covers POR and BOD.
- User Reset: resets caused by the application; it covers External Resets, System Reset Requests, and Watchdog Resets.
The following table lists the parts of the device that are reset, depending on the reset type:
The External Reset is generated when pulling the RESET pin low. The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller (SUPC). The WDT Reset is generated by the Watch Dog Timer (WDT). The System Reset Request is a reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU.
Refer to the "Timing Characteristics" section of the "Electrical Characteristics" chapter from the product data sheet.