PIC32MX Oscillator - Peripheral Bus Clock (PBCLK)

Peripheral Bus Clock (PBCLK)


The peripheral clock is derived from the System Clock (SYSCLK) divided by the peripheral clock divisor setting (÷1, ÷2, ÷4, ÷8).

The peripheral bus frequency can be changed on the fly by writing a new value to the divisor bits. These bits are protected from accidental writes with an unlock sequence. A state machine ensures a stable transition from one clock frequency to another.

PBCLK can also be driven out the CLKO pin.

The default PBCLK divider can be configured at program time and the MPLAB® Harmony functions can be used to configure it at run-time. These functions will perform all unlocking/locking and state machine control for you.

// default PBCLK = SYSCLK/2
#pragma config FPBDIV = DIV_2    
// enable PBCLK
// disable PBCLK
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