PIC32MZ Oscillator - System PLL

The System Phase-Locked Loop (PLL) has a user-selectable input divider, multiplier, and output divider to provide a wide range of output frequencies. The oscillator circuit will consume more current when the PLL is enabled.

System PLL Input Selection


The System PLL can use the Fast RC (FRC) or Primary Oscillators (POSC) as the input.

The default input can be configured at program time and MPLAB® Harmony functions can be used to configure it at run-time.

// Default input is Fast RC Oscillator
#pragma config FPLLICLK = PLL_FRC
// Default input is Primary Oscillator
#pragma config FPLLICLK = PLL_POSC
//Run-time configuration using Harmony functions shown below
// PLL input = FRC
// PLL input = POSC

System PLL Input Divider


System PLL Input divider values include all integers from 1 to 8.

The input divider must be chosen such that the resulting frequency applied to the PLL multiplier is in the range that is specified by the FPLLRNG bits in the Device Configuration (DEVCFG2) register. The FPLLRNG bits can be set to one of the following ranges:

  • 34-64 MHz
  • 21-42 MHz
  • 13-26 MHz
  • 8-16 MHz
  • 5-10 MHz
  • Bypass (input frequency = output)

The default values are programmable and can be changed at run-time.

// default PLL input divider = 1
#pragma config FPLLIDIV = DIV_1
// default PLL input divider = 8 (max)
#pragma config FPLLIDIV = DIV_8
// default multiplier input freq
#pragma config FPLLRNG = 5-10 MHz
// PLL input divider = 1
// PLL input divider = 8

System PLL Multiplier


The multiplier values can be any integer from 1 to 128 and the output of the multiplier must be between 350 and 700 MHz. The PLL multiplier must be configured for the specific input frequency as specified by the FPLLRNG bits.

// default PLL multiply = 1
#pragma config FPLLMULT = MUL_1
// default PLL multiply = 128
#pragma config FPLLMULT = MUL_128
// run-time config sets PLL multiplier to 128 (max)
PLIB_OSC_SysPLLMultiplierSelect(OSC_ID_0, 128);

System PLL Output Divider


The System PLL output clock divider has values from 2 to 32. Ensure the output is between 10 and 200 MHz.

// default PLL output divider = 2
#pragma config FPLLODIV = DIV_2
// default PLL output divider = 32
#pragma config FPLLODIV = DIV_32
// set PLL output divider to 2

System PLL Lock Status

The System PLL requires some time to achieve lock when a clock source is first applied. The SLOCK status bit can be checked to determine if enough time has passed to ensure a stable PLL output.

When the clock input to the PLL is changed, the hardware automatically clears this bit. After the PLL start-up timer has expired, the bit is automatically set. Please refer to the specific device datasheet for PLL lock time ("TLOCK" = 100 us max).

The PLL lock status bit will be set upon the expiration of the timer even if the PLL has not achieved a lock. If the PLL does not stabilize during start-up, SLOCK may not reflect the status of the PLL lock. Similarly, it does not detect when the PLL loses lock during normal operation.

The following MPLAB® Harmony function returns the state of the PLL lock status. You are responsible for checking this status anytime you change the input to the System PLL.

// variable to hold the status of PLL lock
bool clockPLL_st;
// function returns value of PLL lock status
clockPLL_st = PLIB_OSC_PLLClockIsLocked(OSC_ID_0);
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