Read and Write Boot Configuration (bootconfig)

The bootconfig applet reads and writes the Boot Configuration Word (SAMA5D2 Series)/Boot Configuration Packet(SAM9X60).

The bootconfig applet applies to the following devices. Documentation is available in the ../sam-ba/doc/ directory.

bootconfig Command Structure

The bootconfig applet has the following command structure (SAMA5D27 shown in the example below):

* readcfg - read boot configuration
Syntax:
    readcfg:(fuse|bureg0|bureg1|bureg2|bureg3|bscr)
Examples:
    readcfg:fuse    read boot configuration word in fuses
    readcfg:bureg0  read boot configuration word in BUREG0
    readcfg:bscr    read boot sequence register (BSCR)

* writecfg - write boot configuration
Syntax:
    writecfg:(fuse|bureg0|bureg1|bureg2|bureg3|bscr):<configuration>
Examples:
    writecfg:fuse:0x440000       write boot configuration word 0x440000 in fuses
    writecfg:bureg0:0x40fcf      write boot configuration word 0x40fcf in BUREG0
    writecfg:bureg2:QSPI0_IOSET2,EXT_MEM_BOOT  write boot configuration word 0x40001 in BUREG2
    writecfg:bscr:4              write boot sequence register (BUREG0, VALID)
    writecfg:bscr:bureg0,valid   write boot sequence register (BUREG0, VALID)
Configuration value can be either a number or a sequence of tokens separated by commas.
    BSCR tokens:
        BUREG0*, BUREG1, BUREG2, BUREG3 -> to select which BUREG to use
        VALID -> to validate the BSCR and use the selected BUREG
    BUREG/Fuse tokens:
        UART1_IOSET1*, UART0_IOSET1, UART1_IOSET2, UART2_IOSET1, UART2_IOSET2, UART2_IOSET3, UART3_IOSET1, UART3_IOSET2, UART3_IOSET3, UART4_IOSET1, UART_DISABLED,
        JTAG_IOSET1*, JTAG_IOSET2, JTAG_IOSET3, JTAG_IOSET4,
        QSPI0_IOSET1*, QSPI0_IOSET2, QSPI0_IOSET3, QSPI0_DISABLED,
        QSPI1_IOSET1*, QSPI1_IOSET2, QSPI1_IOSET, QSPI1_DISABLED,
        SPI0_IOSET1*, SPI0_IOSET2, SPI0_DISABLED,
        SPI1_IOSET1*, SPI1_IOSET2, SPI1_IOSET3, SPI1_DISABLED,
        NFC_IOSET1*, NFC_IOSET2, NFC_DISABLED,
        SDMMC0*, SDMMC0_DISABLED,
        SDMMC1*, SDMMC1_DISABLED,
        EXT_MEM_BOOT,
        QSPI_XIP_MODE,
        DISABLE_BSCR,
        DISABLE_MONITOR,
        SECURE_MODE,
    Tokens with a star (*) are selected by default if no token from the same line is provided (field value is 0).
    Please refer to SAMA5D2 Datasheet section "16.5 Boot configuration" for information on boot settings.

SAMA5D2 Series Boot Process

The bootconfig applet reads and writes the Boot Configuration Word which can be read from or written to Secure Fuse Controller (SFC) or the Backup Registers (BUREG).

The Boot Process for a device begins with a Processor Reset, followed by the execution of the ROM Boot Code, also known as the Stage One Bootloader. The ROM Boot Code:

• Configures external memories.
• Configures the UART port used as a terminal console.
• Initializes master clock.
• Reads contents to SRAM, if external memory available.

The Boot Configuration Word customizes the Boot Process to:

• Configure I/O where the external memories are connected.
• Enable/disable boot on selected memories.
• Configure the UART port used as a terminal console.
• Configure the JTAG pins used for debug.

Boot Configuration Word Located in Secure Fuse Controller

In a normal production device, the Boot Configuration Word is read from the SFC user area. The SFC contains seventeen 32-bit registers called the Secure Fuse Controller Data Registers (SFC_DRx). One 32-bit word (SFC_DR16) is reserved for the Boot Configuration Word.

After Processor Reset, the ROM Boot Code reads the Boot Configuration Word from SFC_DR16. It checks bit 22 (DISABLE_BSCR), the disable read of Boot Sequence Controller Configuration Register (BSC_CR).

• If the bit is set, the device uses the Boot Configuration Word stored in the Secure Fuse Controller Data Register 16 (SFC_DR16).
• If the bit is cleared, the device reads the Boot Sequence Controller Configuration Register (BSC_CR).

Next, the ROM Boot Code checks the Boot Sequence Controller Configuration Register (BSC_CR) Backup Register Valid (BUREG_VALID) bit.

• If the bit is cleared, the device uses the Boot Configuration Word stored in the SFC.
• If the bit is set, the Boot Configuration Word is contained in one of the four Backup Registers (BUREG).

Finally, the ROM Boot Code reads the BUREG_INDEX from the Boot Sequence Controller Configuration Register (BSC_CR). The device then reads the Boot Configuration Word from the BUREG pointed to by the BUREG_INDEX.

Boot Configuration Word Located in Backup Register

The Boot Configuration Word stored in the SFC can be overridden by the contents of one of the four Backup Registers (BUREG).

To enable reading of the Boot Configuration Word from the Backup Registers, perform the following:

• Secure Fuse Controller Data Register 16, bit 22 (SFC_DR16:22) must be cleared. This is the default factory setting, and
• Boot Sequence Controller Configuration Register (BSC_CR) Backup Register Valid (BUREG_VALID) bit must be set, and
• Backup Register Index bits indicate which BUREG will be used.

Writing a Boot Configuration Word

A Boot Configuration Word can be written to the Secure Fuse Controller or Backup Registers with the following commands:

In this command:

• The Boot Configuration Word is written to the SFC.
• UART1 is selected by default at the target console.
• Boot from external memories is enabled by the EXT_MEM_BOOT bit.
• Selects QSPI0 ioset3 as the external boot memory (as on the SAMA5D2 Xplained Ultra Evaluation Kit).

In this command:

• The Boot Configuration Word is written to the Backup Register 0.
• UART1 is selected by default at the target console.
• Boot from external memories is enabled by the EXT_MEM_BOOT bit.
• Selects SDMMC1 ioset1 and QSPI1 ioset2 as the external boot memory (as on the ATSAMA5D27-SOM1-EK1 evaluation kit).

Reading the Boot Configuration Word

The Boot Configuration Word can be read from the SFC or BUREG with the following commands:

SFC:

BUREG0: