Hardware Limit Timer - Operation

The Hardware Limit Timer (HLT) is similar to any PIC® MCU Timer 2 module. The clock input to the HLT module is the system instruction clock (Fosc/4). The Hardware Limit Timer (HLTMRx) register increments on each rising clock edge. The value of the HLTMRx register is compared to that of the Hardware Limit Timer Period (HLTPRx) register, on each clock cycle. When the two values match, the comparator generates a match signal as the HLTimerx output. This signal also resets the value of HLTMRx to 00h on the next clock rising edge and drives Complimentary Output Generator (COG) output along with the output counter/postscaler.


The HLT can be turned off or on at any point by clearing or setting the HLT On bit in the Hardware Limit Timer Control 0 (HLTxCON0) register. The clock input to the HLT can be slowed down by using the optional 4-bit counter/prescaler at the clock input. This prescaler provides the following prescale options:

• Divide-by-1
• Divide-by-4
• Divide-by-16
• Divide-by-64

The prescale options are selected by the prescaler control bits, HxCKPS<1:0> of the HLTxCON0 register. The output of the HLT can be directed to the COG module and also to the HLT output postscaler. The postscaler can also be set to delay the HLT Interrupt from one match on up to 16 matches. This is selected by the HxOUTPS<3:0> bits in the HLTxCON0 register.



The HLTMRx and HLTPRx registers are both directly readable and writable. The HLTMRx register is cleared on any device Reset, whereas the HLTPRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on any of the following events:

  • A write to the HLTMRx register
  • A write to the HLTxCON0 register
  • Power-On Reset (POR)
  • Brown-Out Reset (BOR)
  • MCLR Reset
  • Watchdog Timer (WDT) Reset
  • Stack Overflow Reset
  • Stack Underflow Reset
  • RESET Instruction
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