Hardware Limit Timer - Resets

The Hardware Limit Timer (HLT) can be reset by several selected peripheral outputs to prevent the Hardware Limit Timer (HLTMRx) register from matching the Hardware Limit Timer Period (HLTPRx) register and generating an output. In this manner, the HLT can be used as a hardware time limit to other peripherals.

The HLTMRx can be reset by one of several selectable peripheral sources:

  • CCP1 output
  • Comparator 1 output
  • Comparator 2 output
  • COGxFLT pin
  • COG1OUT0
  • COG1OUT1

The HLT can be reset by various external sources which are selected via the HLT External Reset Sources Select bits (HxERS <2:0>) in the HLT Control 1 (HLTxCON1) register. The edge sensitivity can also be selected with the HLTxCON1 register. High and low reset enables are selected with the Hardware Limit Timerx Rising Event Reset Enable (HxREREN) bit and Hardware Limit Timerx Failing Event Reset Enable (HxFEREN) bit, respectively. Setting the Hardware Limit Timerx Rising Edge Sensitivity (HxRES) and Hardware Limit Timerx Falling Edge Sensitivity (HxFES) bits make the respective rising and falling reset events edge sensitive. Reset inputs that are not edge sensitive are level sensitive.

HLTMRx resets are synchronous with the HLT clock. In other words, HLTMRx is cleared on the rising edge of the HLT clock after the enabled reset event occurs. If an enabled external reset occurs at the same time as a write occurs to the HLTMRx register, the write to the timer takes precedence and pending resets are cleared.



HLT Operation During Sleep

The HLT cannot be operated while the processor is in Sleep mode. The contents of the HLTMRx register will remain unchanged while the processor is in Sleep mode.

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