Watchdog Timer Reset (WDT)

The WDT is similar to the Master Clear External Reset as it will hold a PIC® MCU in reset when activated and place the Program Counter back to the beginning of the program software (org 0). The WDT is activated when its time-out period is exceeded. It is a free running timer independent of the main system clock. If the operation of the code in the device is affected by an external source that causes the software to deviate from its expected path, the WDT may be able to reset the device automatically depending how the reset is used in the design. The software designer can place instructions to clear the WDT counter and prevent a WDT reset from occurring. It's when those instructions are not executed, such as when an external interference affects the proper operation, that the WDT will engage and reset the device.

The WDT can be enabled or disabled in a configuration setting or even under software control.

Features Include:

  • Independent Clock Source
  • Multiple Operating Modes
    • WDT Always On
    • WDT Off in Sleep
    • WDT Controlled by Software
    • WDT Always Off
  • Configurable Time-Out Period from 1 millisecond to 256 seconds
  • Multiple Reset Conditions
  • Operation During Sleep

WDT Prescaler

The WDT is essentially a counter that is incremented on each clock pulse. The prescaler can be set to a value that determines the number of clock pulses to cause the reset. When the WDT is cleared, the counter in the prescaler is cleared back to zero and the time count starts all over.

WDT Indicator Bits

The RWDT = 0 and TO = 0 bits in the Status register will be cleared when a Watchdog Timeout Reset occurred during normal operation.

WDT Operating Modes

The WDT has four operating modes:

  • WDT Always On
  • WDT Off in Sleep
  • WDT Controlled by Software
  • WDT Off

Two bits in a configuration register control the mode for the WDT. Those bits are the WDTE bits shown below.


WDT Always On

The WDT is always operating when this mode is selected, even during sleep.

WDT Off in Sleep

The WDT is on except when the device is put to sleep when this mode is selected.

WDT Controlled by Software

The WDT can be enabled or disabled in software when this mode is selected. The SWDTEN bit of the WDTCON register can be set or cleared to enable or disable the WDT.


The WDT is disabled and cannot reset the device.


Time-Out Period

The WDT derives its time base from the 31khz Low Frequency Internal Oscillator (LFINTOSC). This oscillator runs independently of the system clock (unless the LFINTOSC is selected as the system oscillator as well).

The WDT timeout can be set with the Watchdog Timer Period Select Bits (WDTPS) in the Watchdog Timer Control Register (WDTCON). Five bits select the timer period ranging from 1 Millisecond to 256 seconds.

The Register and WDPTS bits are shown below.


Clearing the WDT

Unlike other reset options, the WDT can be prevented form occurring via software control. This occurs by clearing the watchdog counter before it hits the timeout mark. The WDT counter can also be reset by other means automatically.

Below is a list of ways the the WDT counter is reset:

  • Any Reset other than WDT will clear the WDT counter
  • The clrwdt assembly instruction will clear the WDT counter
  • When the device enters sleep mode the WDT counter is cleared
  • When the device wakes up from sleep the WDT counter is cleared
  • When the WDT is disabled the WDT counter is cleared
  • When the Oscillator Start-up Timer is running the WDT counter is cleared

All of these conditions, except for the clrwdt instruction, automatically clear the WDT counter.

Operation During Sleep

When the device enters sleep mode the WDT counter is cleared. If the WDT is enabled for operation during sleep then the WDT counter continues incrementing on each clock pulse.

When the device exits from sleep mode the WDT counter is reset again and continues counting if enabled.

When the WDT times-out in sleep mode, a reset will not reset the program counter but instead just wake the device up from sleep. Operation will continue at the instruction placed after the sleep instruction that put the device into sleep mode originally.

The POR = 0 and TO = 0 bits in the Status register will be cleared to indicate a wake-up from sleep was caused by the WDT time-out.

For more information on 8-bit reset options visit the Reset Options wiki page.

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