Hardware User's Guide for USB Power Delivery Software Framework Evaluation Kit

Functional Block Diagram

EVB-PSF is a full-fledged PD development platform that can be used to implement multiple PD ports and support a variety of power and data roles using PSF. Figure 3-1 shows the various functional blocks of this platform.

Figure-3-1.png
Figure 3-1 Functional Block Diagram

SAMD20 Connectors

The onboard ATSAMD20E16A serves as the main MCU for running the PSF software stack. It is used to manage the port policy of both PD ports through the UPD350 PD PHY. The PSF pin functions assigned to the SAMD20 pins can be summarized as follows:

Figure-3-2.png
Figure 3-2: SAMD20 Connector J10 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J10 Ground 1 2 Ground N Spare Ground pins, not connected to SAMD20
RESET_N0_OUT 3 4 PA00 Y RESET_N0_OUT is used to control the reset lines of the UPD350s. Assigned to PA00 of SAMD20 by default.
SPI_SS1 5 6 PA01 Y SPI_SS1 is used to control the SPI chip select of the Port 2 UPD350. Assigned to PA01 of SAMD20 by default.
DC_DC_ALERT0 7 8 PA02 Y DC_DC_ALERT0 is the IRQ line of the Port 1 I2C mode PM-PD module. Assigned to PA02 of SAMD20 by default
DC_DC_ALERT1 9 10 PA03 Y DC_DC_ALERT1 is the IRQ line of the port 2 I2C mode PM-PD module. Assigned to PA03 of SAMD20 by default
GPIO4 11 12 PA04 Y Free GPIO, NC
GPIO5 13 14 PA05 Y Free GPIO, NC
I2C_SLAVE_IRQ 15 16 PA06 Y I2C_SLAVE_IRQ is the IRQ line for the SAMD20 I2C slave interface. Assigned to PA06 of SAMD20 by default.
GPIO7 17 1 8 PA07 Y Free GPIO, NC
Ground 19 20 Ground N Spare Ground Pins, not connected to SAMD20
Figure-3-3.png
Figure 3-3: SAMD20 Connector J9 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J9 Ground 1 2 Ground N Spare Ground pins, not connected to SAMD20
GPIO27 3 4 PA27 Y Free GPIO, NC
RESET_N1_IN 5 6 RESET Y RESET_N1_IN is the global reset line used to control the SAMD20 reset line
GPIO28 7 8 PA28 Y Free GPIO, NC
Ground 9 10 Ground Y Connects the SAMD20 ground to the system ground
VDD12_CORE 11 12 VDDCORE Y Connects the internal 1.2V regulator output of the SAMD20 to TP2
VSW_SAM 13 14 VDDIN Y Powers the SAMD20 VDDIN pin from 3.3V VSW_SAM rail
TRGT_SWCLK 15 16 PA30 Y Connects the external/onboard programmer debugger clock line to SWD interface of SAMD20. Assigned to PA30 of SAMD20 by default
TRGT_SWDIO 17 18 PA31 Y Connects the external/onboard programmer debugger data line to SWD interface of SAMD20. Assigned to PA31 of SAMD20 by default
Ground 19 20 Ground N Spare Ground Pins, not connected to SAMD20
Figure-3-4.png
Figure 3-4: SAMD20 Connector J11 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J11 Ground 1 2 Ground N Spare Ground pins, not connected to SAMD20
I2C_SLAVE_SDA 3 4 PA16 Y I2C_SLAVE_SDA is the data line of the SAMD20 I2C Slave interface. Assigned to PA16 of SAMD20 by default
I2C_SLAVE_SCL 5 6 PA17 Y I2C_SLAVE_SCL is the clock line of the SAMD20 I2C Slave interface. Assigned to PA17 of SAMD20 by default
TRACE_TX 7 8 PA18 Y TRACE_TX is the transmit line of the UART debug interface. Assigned to PA18 of the SAMD20 by default
TRACE_RX 9 10 PA19 Y TRACE_RX is the receive line of the UART debug interface. Assigned to PA19 of the SAMD20 by default
I2C_MASTER_SDA 11 12 PA22 Y I2C_MASTER_SDA is the data line of the SAMD20 I2C Master interface. Used to control PM-PD modules. Assigned to PA22 of SAMD20 by default
I2C_MASTER_SCL 13 14 PA23 Y I2C_MASTER_SCL is the clock line of the SAMD20 I2C Master interface. Used to control PM-PD modules. Assigned to PA23 of SAMD20 by default
GPIO24 15 16 PA24 Y Free GPIO, NC, external pull-ups
GPIO25 17 18 PA25 Y Free GPIO, NC, external pull-ups
Ground 19 20 Ground N Spare Ground Pins, not connected to SAMD20
Figure-3-5.png
Figure 3-5: SAMD20 Connector J12 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J12 Ground 1 2 Ground N Spare Ground pins, not connected to SAMD20
VSW_SAM 3 4 VDDANA Y Powers the SAMD20 VDDANA pin from 3.3V VSW_SAM rail
Ground 5 6 Ground Y Connects the SAMD20 ground to the system ground
SPI_MISO 7 8 PA08 Y Connects the SPI bus to the MISO pin of the SAMD20. Assigned to PA08 of SAMD20 by default
SPI_CLK 9 10 PA09 Y Connects the SPI bus to the SPI clock pin of the SAMD20. Assigned to PA09 of SAMD20 by default
SPI_SS0 11 12 PA10 Y SPI_SS0 is the SPI chip select line of Port 1. Assigned to PA10 of SAMD20 by default
SPI_MOSI 13 14 PA11 Y Connects the SPI bus to the SPI MOSI pin of the SAMD20. Assigned to PA11 of SAMD20 by default
SPI_IRQ_N0 15 16 PA14 Y SPI_IRQ_N0 is the SPI interrupt line for Port 1. Assigned to PA14 of SAMD20 by default. External pull-up present.
SPI_IRQ_N1 17 18 PA15 Y SPI_IRQ_N1 is the SPI interrupt line for Port 2. Assigned to PA15 of SAMD20 by default. External pull-up present.
Ground 19 20 Ground N Spare Ground Pins, not connected to SAMD20

UPD350 Connectors

Each PD Port is controlled by a dedicated UPD350B PD PHY. The UPD350B serve as SPI slaves and are managed by the onboard SPI Master, i.e., SAMD20. The PSF pin functions assigned to the Port 1 UPD350 pins are summarized below:

Figure-3-6.png
Figure 3-6: UPD350 Connector J5 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J5 CC2_P1 1 2 CC2 Y Connects the CC2 line of PD port 1 to CC2 pin of the Port 1 UPD350
5V_BRD 3 4 VCONN_P1 Y Connects the +5V board supply to the VCONN input of the Port 1 UPD350. VCONN is needed for active Type-CTM cables
CC1_P1 5 6 CC1 Y Connects the CC1 line of PD port 1 to CC1 pin of the Port 1 UPD350
VBUS_DET_IN_P1 7 8 VBUS_DET Y Connects the sampled (through 10% voltage divider) VBUS voltage of Port 1 to the VBUS_DET pin of Port 1 UPD350
Ground 9 10 CFG_SEL Y Connects the CFG_SEL pin of port 1 UPD350 to ground.
ISENSE_UP1 11 12 OCS_COMP1 Y Connects the current sense output of Port 1 PM-PD module to internal OCS comparator 1 of Port 1 UPD350
Ground 13 14 PWR_DN Y Grounds the PWR_DN pin of the Port 1 UPD350. If this pin is asserted, UPD350 will enter power down state. This pin should not be left floating for proper operation
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-7.png
Figure 3-7: UPD350 Connector J1 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J1 RESET_N0_OUT 1 2 RESET_N_P1 Y Connects the RESET_N0_OUT output of the SAMD20 to the Port 1 UPD350 reset line
VBUS_DIS_P1 3 4 PIO04_P1 Y VBUS_DIS_P1 is used to control the VBUS discharge FET of Port 1. Assigned to PIO04 of Port 1 UPD350 by default
FAULT_IN_N_P1 5 6 PIO05_P1 Y FAULT_IN_N_P1 is the fault notification from Port 1 PM-PD module. Assigned to PIO05 of Port 1 UPD350 by default. External pull up present
DC_DC_EN_P1/ EN_SINK_P1 7 8 PIO06_P1 Y DC_DC_EN_P1 is used to enable the Port 1 PM-PD module. EN_SINK_P1 is used to enable the Sink mode load switch of Port 1. Refer J15 for more details. Assigned to PIO06 of Port 1 UPD350 by default
VSEL0_EN_9V_P1 9 10 PIO07_P1 Y VSEL0_EN_9V_P1 is used to control the VSEL0 input of the Port 1 GPIO mode PM-PD module. Assigned to PIO07 of Port 1 UPD350 by default. External pull-down present
VSEL1_EN_15V_P1 11 12 PIO08_P1 Y VSEL1_EN_15V_P1 is used to control the VSEL1 input of the Port 1 GPIO mode PM-PD module. Assigned to PIO08 of Port 1 UPD350 by default. External pull-down present
VSEL2_EN_20V_P1 13 14 PIO09_P1 Y VSEL2_EN_20V_P1 is used to control the VSEL2 input of the Port 1 GPIO mode PM-PD module. Assigned to PIO09 of Port 1 UPD350 by default. External pull-down present
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-8.png
Figure 3-8: UPD350 Connector J4 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J4 SPI_MISO 1 2 SPI_DO_P1 Y Connects the MISO line of the SPI bus to SPI_DO pin of the Port 1 UPD350
SPI_CLK 3 4 PIO00_P1 Y Connects the clock line of the SPI bus to the SPI_CLK/PIO00 pin of the Port 1 UPD350
SPI_SS0 5 6 PIO01_P1 Y Connects the Port 1 SPI chip select line from SAMD20 to SPI_CS_N/PIO01 pin of Port 1 UPD350. External pull-up present
ORIENTATION_N_P1 7 8 PIO02_P1 Y ORIENTATION_N_P1 is used to control the Port 1 super speed MUX direction as well as the Port 1 Orientation status LED. Assigned to PIO02 of Port 1 UPD350 by default. External pull-up present
EN_VBUS_P1 9 10 PIO03_P1 Y EN_VBUS_P1 is used to control the source mode load switch of Port 1. Assigned to PIO03 of Port 1 UPD350 by default
NC 11 12 VPP N VPP is the +1.8 V power supply input of the UPD350. Tied to VDD18 pin through PCB trace.
SPI_IRQ_N0 13 14 IRQ_N_P1 Y Connects SPI_IRQ_N0 from SAMD20 line to the IRQ_N pin of the port 1 UPD350. External pull-ups present
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-9.png
Figure 3-9: UPD350 Connector J8 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J8 3V3_BRD 1 2 VDD33_ALWAYS_P1 Y Connects the 3V3_BRD supply to the always-on power supply input of port 1 UPD350
3V3_VSW 3 4 VDD33_VSW_P1 Y Connects the output of the internal power switch of the port 1 UPD350 to the 3V3_VSW board supply net
3V3_DB 5 6 VDD33_VBUS_P1 Y Connects the 3V3_DB supply to the VBUS power supply input of the port 1 UPD350
VDD18_P1 7 8 VDD18_CORE_P1 Y Connects the +1.8 V internal voltage regulator output to TP10. Also tied to VPP pin of UPD350 through PCB trace
3V3_VSW 9 10 VDDIO_P1 Y Connects the VDDIO pin of port 1 UPD350 to the internal power switch output 3V3_VSW
SPI_MOSI 11 12 SPI_DI_P1 Y Connects the MOSI line of the SPI bus to SPI_DI pin of the Port 1 UPD350
Ground 13 14 Ground N Spare Ground Pins, not connected to UPD350
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-10.png
Figure 3-10: UPD350 Connector J6 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J6 CC2_P2 1 2 CC2 Y Connects the CC2 line of PD port 2 to CC2 pin of the Port 2 UPD350
5V_BRD 3 4 VCONN_P2 Y Connects the +5 V board supply to the VCONN input of the Port 2 UPD350. VCONN is needed for active Type-CTM cables
CC1_P2 5 6 CC1 Y Connects the CC1 line of PD port 1 to CC1 pin of the Port 2 UPD350
VBUS_DET_IN_P2 7 8 VBUS_DET Y Connects the sampled (through 10% voltage divider) VBUS voltage of Port 2 to the VBUS_DET pin of Port 2 UPD350
Ground 9 10 CFG_SEL Y Connects the CFG_SEL pin of port 2 UPD350 to ground.
ISENSE_UP2 11 1 2 OCS_COMP1 Y Connects the current sense output of Port 2 PM-PD module to internal OCS comparator 1 of Port 2 UPD350
Ground 13 14 PWR_DN Y Grounds the PWR_DN pin of the Port 2 UPD350. If this pin is asserted, UPD350 will enter power down state. This pin should not be left floating for proper operation
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-11.png
Figure 3-11: UPD350 Connector J2 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J2 RESET_N0_OUT 1 2 RESET_N_P2 Y Connects the RESET_N0_OUT output of the SAMD20 to the Port 2 UPD350 reset line
VBUS_DIS_P2 3 4 PIO04_P2 Y VBUS_DIS_P2 is used to control the VBUS discharge FET of Port 2. Assigned to PIO04 of Port 2 UPD350 by default
FAULT_IN_N_P2 5 6 PIO05_P2 Y FAULT_IN_N_P2 is the fault notification from Port 2 PM-PD module. Assigned to PIO05 of Port 2 UPD350 by default. External pull up present
DC_DC_EN_P2/ EN_SINK_P2 7 8 PIO06_P2 Y DC_DC_EN_P2 is used to enable the Port 2 PM-PD module. EN_SINK_P2 is used to enable the Sink mode load switch of Port 2. Refer J15 for more details. Assigned to PIO06 of Port 2 UPD350 by default
VSEL0_EN_9V_P2 9 10 PIO07_P2 Y VSEL0_EN_9V_P2 is used to control the VSEL0 input of the Port 2 GPIO mode PM-PD module. Assigned to PIO07 of Port 2 UPD350 by default. External pull-down present
VSEL1_EN_15V_P2 11 12 PIO08_P2 Y VSEL1_EN_15V_P2 is used to control the VSEL1 input of the Port 2 GPIO mode PM-PD module. Assigned to PIO08 of Port 2 UPD350 by default. External pull-down present
VSEL2_EN_20V_P2 13 14 PIO09_P2 Y VSEL2_EN_20V_P2 is used to control the VSEL2 input of the Port 2 GPIO mode PM-PD module. Assigned to PIO09 of Port 2 UPD350 by default. External pull-down present
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-12.png
Figure 3-12: UPD350 Connector J3 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J3 SPI_MISO 1 2 SPI_DO_P2 Y Connects the MISO line of the SPI bus to SPI_DO pin of the Port 2 UPD350
SPI_CLK 3 4 PIO00_P2 Y Connects the clock line of the SPI bus to the SPI_CLK/PIO00 pin of the Port 2 UPD350
SPI_SS1 5 6 PIO01_P2 Y Connects the Port 2 SPI chip select line from SAMD20 to SPI_CS_N/PIO01 pin of Port 2 UPD350. External pull-up present
ORIENTATION_N_P2 7 8 PIO02_P2 Y ORIENTATION_N_P2 is used to control the Port 2 super speed MUX direction as well as the Port 2 Orientation status LED. Assigned to PIO02 of Port 2 UPD350 by default. External pull-up present
EN_VBUS_P2 9 10 PIO03_P2 Y EN_VBUS_P2 is used to control the source mode load switch of Port 2. Assigned to PIO03 of Port 2 UPD350 by default
NC 11 12 VPP N VPP is the +1.8V power supply input of the UPD350. Tied to VDD18 pin through PCB trace.
SPI_IRQ_N1 13 14 IRQ_N_P2 Y Connects SPI_IRQ_N1 from SAMD20 line to the IRQ_N pin of the port 2 UPD350. External pull-ups present
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350
Figure-3-13.png
Figure 3-13: UPD350 Connector J7 Pin out
Connector PSF Signal Name Pin Number SAMD20 Pin name Jumper Populated Description
J7 3V3_BRD 1 2 VDD33_ALWAYS_P2 Y Connects the 3V3_BRD supply to the always-on power supply input of port 2 UPD350
3V3_VSW 3 4 VDD33_VSW_P2 Y Connects the output of the internal power switch of the port 2 UPD350 to the 3V3_VSW board supply net
3V3_DB 5 6 VDD33_VBUS_P2 Y Connects the 3V3_DB supply to the VBUS power supply input of the port 2 UPD350
VDD18_P2 7 8 VDD18_CORE_P2 Y Connects the +1.8 V internal voltage regulator output to TP11. Also tied to VPP pin of UPD350 through PCB trace
3V3_VSW 9 10 VDDIO_P2 Y Connects the VDDIO pin of port 2 UPD350 to the internal power switch output 3V3_VSW
SPI_MOSI 11 12 SPI_DI_P2 Y Connects the MOSI line of the SPI bus to SPI_DI pin of the Port 2 UPD350
Ground 13 14 Ground N Spare Ground Pins, not connected to UPD350
Ground 15 16 Ground N Spare Ground Pins, not connected to UPD350

PM-PD

EVB-PSF ships with two PM-PD modules (PMPD-VM_HOT) which are rated for 60 W. These modules are needed for configuring the PD ports in Source or DRP mode. The PM-PD modules consists of Microchip’s MCP19119 DEPA buck DC-DC power supply and the source mode load switch, which is capable of 3A output. Refer to the "PM-PD Power Supply" section for more information on the input power requirements of these modules.

Figure 3-14 shows the correct way of installing the PM-PD modules on headers J35 and J44.

DO NOT plug-in or remove the PM-PD modules while the EVB-PSF is powered ON.

Ensure that all the pins of the PM-PD modules are aligned and inserted properly before turning on the power supply.

Figure-3-14.png
Figure 3-14: Installing PM-PD modules on J35 and J44

GPIO Mode

GPIO mode PM-PDs should be connected to headers J35 and J44 on the EVB-PSF. The PMPD-VM-HOT modules provided in the evaluation kit are controlled by GPIOs and work in “One-Hot” mode where the voltage output is determined by the following truth table:

Output Voltage VSEL0 VSEL1 VSEL2
5 V 0 0 0
9 V 1 0 0
15 V 0 1 0
20 V 0 0 1

When connected to the EVB-PSF, the PM-PD modules are configured by default to output 5 V because of weak pull-downs on the VSEL[0:2] and DC_DC_EN pins. Although, 5 V will be available on the PD port only when the load switch is turned on by PSF.

I2C Mode

EVB-PSF also supports DC-DC modules which can be controlled through I2C. These modules can be plugged into headers J34 and J43. The I2C headers on EVB-PSF are depopulated by default. For more information regarding I2C mode PM-PDs, contact Microchip Support.

GPIO mode and I2C mode cannot be supported simultaneously.

PD Ports

EVB-PSF consists of two full-featured USB Type-CTM ports (J29 and J32) which can be configured in PD Source, Sink, or DRP modes with USB Data. These ports support USB 3.1 (Gen1 and Gen2) as well as USB 2.0 (HS, FS, and LS operation). In Sink/DRP mode, these ports can be self-powered, or bus powered.

USB Data Pass-through and Multiplexing

EVB-PSF comes with two USB 3.1 Type-A data pass-through ports (USB3.1 Gen1/Gen2, USB2.0) which can connect to a USB host or device. These ports can be used to route USB data to the port partner connected to the Type-CTM PD port. USB3 lanes are routed through a USB3.1 Gen 1/Gen2 compliant mux which is controlled by the ORIENTATION_N signal of the UPD350 to resolve the Type-CTM orientation.

Sink Output Terminals and Sink Mode Load Switch

SINK_TERM1 (J37) is the sink output terminal for PD port 1 which can be used to connect an external load in case of PD Sink/DRP mode. When the Sink mode load switch consisting of MOSFETs Q2, Q3, and Q5 are turned ON by PSF, the negotiated PD voltage on VBUS of PD Port 1 (J29) will be available on SINK_TERM1 (J37).

SINK_TERM2 (J42) is the sink output terminal for PD port 2 which can be used to connect an external load in case of PD sink/DRP mode. When the Sink mode load switch consisting of MOSFETs Q7, Q8, and Q10 are turned ON by PSF, the negotiated PD voltage on VBUS of PD Port 2 (J32) will be available on SINK_TERM2 (J42).

Power Supplies

EVB-PSF offers a lot of flexibility in powering the board. The following board power supply block diagram in Figure 3-15 illustrates the various power supply options available.

Figure-3-15.png
Figure 3-15: Board Supply Power Block Diagram

Board Power Supply

DC-IN and VIN

DC_IN (J49) is the main power supply connector for powering the whole kit in self-powered mode. A male plug is provided for easy interfacing with a bench supply. DC_IN input supply can range from +10 VDC to +24 VDC (regulated). An onboard slow acting fuse F1 is provided for overcurrent protection from input steady state currents above 7 A.

EVB-PSF also has an onboard soft-start circuit to keep the inrush currents in check and ensure a controlled monotonic rise time for preventing overshoots above 26 VDC. VIN is derived from DC_IN and it powers all the onboard power supply regulators. It can also be used to power the two PM-PD modules. Refer to the "Single Supply Options" section for more information.

+5 VDC

The onboard MCP19035 (U11) with the onboard MOSFETs (Q13 and Q15) is used to step down the wide-ranging VIN input to power the 5V_BRD rail of the board. This 5 V DC rail provides the 5V required for VCONN of the two PD ports in Source/DRP mode, USB3 muxes, and powers the onboard MCP6C02 (U20 and U21) current sense amplifiers, which are a part of the LED current meters.

+3.3 VDC

The various 3.3 VDC supply rails are summarized in table below:

3.3VDC Rail Description
3V3_BRD In self-powered state, EVB-PSF uses the onboard MCP1825 (U13) to provide 3V3_BRD supply and is rated for 500 mA. This LDO is powered by the 5V_BRD supply rail.
3V3_DB In bus powered mode (PD Sink or DRP), EVB-PSF uses the onboard MCP1804 (U14) to provide 3V3_DB supply. This LDO is powered directly from the VBUS_OR supply, which is derived by ORing the VBUS1 and VBUS2 of the PD ports. The 3V3_DB rail is rated for 150 mA.
3V3_VSW This is the output of the internal power switch of the UPD350. It is used to power the critical components (like SAMD20, RESET supervisor, and LED voltage and current meters) on the board to allow for PD negotiation in a bus-powered or dead battery state.
VSW_SAM VSW_SAM is derived from the 3V3_VSW output of the UPD350 and is used to exclusively power the onboard SAMD20 and the Reset Supervisor.

In bus-powered mode, the 3V3_DB supply can provide up to 150 mA, but the power rail capacity is limited to 100 mA by the internal power supply selection switch of the UPD350

PM-PD Power Supply

The PM-PD modules can be powered independently of the main board supply by using the HV_IN1 (J36) and HV_IN2 (J45) terminal blocks as shown in Figure 3-16. HV_IN1 and HV_IN2 supply ranges are dependent on the requirements of the DC-DC converter module used and the PDOs configured in the PSF software stack.

The PMPD-VM-HOT modules provided as part of the kit need +24 VDC input for supplying the standard PDOs of 5 V, 9 V, 15 V, and 20 V.

Figure-3-16.png
Figure 3-16: PM-PD Supply Power Block Diagram

Single Supply Options

The single supply option jumpers on the EVB-PSF as shown in Figure 3-17 allow for flexible routing of power on the board in self-powered and bus-powered modes. Figures 3-15 and 3-16 show the flexibility provided by these jumper options. The following table summarizes the various single supply options available:

Header Jumper
Placement
Default State Description
J38 1-2
3-4
4-5
Populated When all the jumpers are installed, this option ties HV_IN1 to VIN and allows Port 1 PM-PD module to be powered from the main board supply VIN
J39 1-2
3-4
5-6
Populated When all the jumpers are installed, this option ties HV_IN2 to VIN and allows Port 2 PM-PD module to be powered from the main board supply VIN
J40 1-2
3-4
5-6
Open When all the jumpers are installed, this option ties HV_IN1 to HV_IN2. This option allows both the PMPD modules to be powered from a common power supply. The common PMPD power supply input can be connected on either J36 or J45 terminal blocks. If J38 and J39 are left unpopulated along with this option enabled, the PM-PDs and the rest of the board can be powered independently from different power supplies
Figure-3-17.png
Figure 3-17: Single Supply and Bus Power Options

Bus Power Options

The bus power jumper options on the EVB-PSF as shown in Figure 3-17 allows the board to be powered from the negotiated VBUS voltage in PD Sink or DRP mode. The following table summarizes the various bus power single supply options available:

Header Jumper
Placement
Default Description
J47 1-2
3-4
Open When all the jumpers are installed, this option ties SINK_TERM1 to VIN. This option powers the whole board using the negotiated VBUS voltage of Port 1 in Sink mode
J48 1-2
3-4
Open When all the jumpers are installed, this option ties SINK_TERM2 to VIN. This option powers the whole board using the negotiated VBUS voltage of Port 2 in Sink mode

Reset

SAMD20 Reset

The SAMD20 RESET pin is controlled by the following sources:

Reset Source Description
Reset Supervisor (U5) Onboard MIC803 controls the RESET line by monitoring the VSW_SAM rail that powers the SAMD20. Reset is asserted if the VSW_SAM < 2.93 V.
Reset Switch (SW1) SW1 pulls the RESET line low by shorting it to ground
Reset Header (J18) J18 is a 1x2 header that connects the RESET to ground when populated.
PKoB Nano (U6) When DBG_SEL (J20) has a jumper populated across pins 1-2, the onboard programmer/debugger will control the RESET line.
Refer ICE Programming section for more information on J20
External Debugger (J19) When DBG_SEL (J20) has a jumper populated across pins 2-3, an external debugger connected on ICE interface (J19) will control the RESET line.
Refer ICE Programming section for more information on J20

UPD350 Reset

The RESET_N line of the UPD350 (U1, U2) is controlled by the RESET_N0_OUT (J10-3) of SAMD20 (U3). PA00 (Pin 1) is assigned RESET_N0_OUT function in PSF by default. Any SAMD20 GPIO can be assigned the RESET_N0_OUT function in software and the corresponding pin on the EVB can be connected to RESET_N0_OUT (J10-3) using a fly wire.

LED Indicators

Power Supply Status LEDs

The power supply status LEDs are shown in Figure 3-18 and summarized in the table below:

LED Function Color Description
D12 “VIN” Orange When ON, indicates the presence of +10-26 V on DC_IN and VIN rails
D13 “5V” Green When ON, indicates that the +5 V regulator is functional and +5 V is present on 5V_BRD rail.
D16 “3V3” Green When ON, indicates that the +3.3 V regulator is functional and +3.3 V is present on 3V3_BRD rail.
D17 “3V3_DB” Green When ON, indicates that the bus-powered +3.3 V regulator is functional and +3.3 V is present on 3V3_DB rail.
Figure-3-18.png
Figure 3-18: Power Supply Status LEDs

Signal LEDs

The signal status LEDs for ports 1 and 2 are shown in Figure 3-19 and summarized in the table below:

LED Function Default State: Color Description
D18, D31 (dual color) “ORIENT_N” ON : Green (default) Indicates the Type-CTM connection orientation for PD ports 1 and/or 2. Orientation 1 corresponds to Green and Orientation 2 corresponds to Red.
D21, D34 “VBUS_DIS” OFF : Yellow When ON, indicates that the VBUS discharge FETs (Q4, Q9) are enabled for ports 1 and/or 2. Applies to PD Source and DRP modes.
D22, D35 “VBUS_EN” OFF : Yellow When ON, indicates that the VBUS source mode load switches (on PM-PDs) are enabled for ports 1 and/or 2. Applies to PD source and DRP modes.
D24, D36 “SINK_EN” OFF : Yellow When ON, indicates that the VBUS Sink mode load switches (Q5, Q10) are enabled for ports 1 and/or 2. Applies to PD sink and DRP modes.
D26, D37 “DC_DC_EN” ON : Yellow When ON, indicates that the DC-DC modules for ports 1 and/or 2 are enabled. Applies to PD source and DRP modes
D27, D38 “FAULT_IN_N” OFF : Yellow When ON, indicates that a fault condition was encountered by the DC-DC modules for ports 1 and/or 2. Applies to PD source and DRP modes.
D28, D39 “SPI_IRQ_N” OFF: Yellow When ON, indicates that a fault condition was encountered in the SPI communication between the SAMD20 and UPD350 of port 1 and/or 2. SPI_IRQ_Nx go low when there is an un-serviced SPI interrupt. Applies to all PD modes

LEDs D26 and D37 will stay ON in all PD modes because of weak pull-ups on DC_DC_EN lines.

Figure-3-19.png
Figure 3-19: Signal Status LEDs

VBUS Voltage and Current Meters

EVB-PSF provides a visual indication of the PD port voltage and current through a dedicated LED voltage and current meter for ports 1 and 2.

The VBUS voltage is sensed using a 10% resistor divider and compared against four different reference voltages using a MCP6549, 4-channel comparator.

The VBUS current is sensed using a 4 mΩ shunt resistor and measured using a MCP6C02 high side current sense amplifier. The output of the MCP6C02 is then compared against four different voltage using a MCP6549, 4-channel comparator.

VBUS Voltage and Current meters provide only an approximate indication of the negotiated VBUS voltage and current. We recommend using a digital multi-meter and/or PD analyzer for accuracy.

The VBUS voltmeter LEDs for the ports 1 and 2 are shown in Figure 3-20 and summarized in the table below:

LED Function Default State: Color Description
D19, D20 “5V” OFF : Green When ON, it indicates the presence of 5 V on VBUS line of Port 1 and/or 2
D23, D25 “9V” OFF : Yellow When ON, it indicates the presence of 9 V on VBUS line of Port 1 and/or 2
D29, D30 “15V” OFF : Orange When ON, it indicates the presence of 15 V on VBUS line of Port 1 and/or 2
D32, D33 “20V” OFF : Red When ON, it indicates the presence of 20 V on VBUS line of Port 1 and/or 2

The VBUS voltmeters are bi-directional. They are functional in PD Source, Sink, and DRP modes.

Figure-3-20.png
Figure 3-20: VBUS LED voltage and current meters

The VBUS current meters LEDs for the ports 1 and 2 are shown in Figure 3-20 above and summarized in the table below:

LED Function Default State: Color Description
D40, D41 “0.5A” OFF : Green When ON, it indicates that the port 1 and/or 2 VBUS line is sourcing 0.5 A
D42, D43 “1.5A” OFF : Yellow When ON, it indicates that the port 1 and/or 2 VBUS line is sourcing 1.5 A
D44, D45 “3A” OFF : Orange When ON, it indicates that the port 1 and/or 2 VBUS line is sourcing 3 A
D46, D47 “5A” OFF : Red When ON, it indicates that the port 1 and/or 2 VBUS line is sourcing 5 A

The VBUS current meters are unidirectional. They are functional only when the PD ports are sourcing a current in PD Source or DRP mode.

USB Pass-through VBUS LEDs

Figure 3-21 shows the VBUS LEDs for USB data pass-through ports 1 and 2.

LED Function Default State: Color Description
D4 “PASS-THRU VBUS1” OFF : Green When ON, this LED indicates the presence of 5VDC on the VBUS line of the data passthrough port 1. This LED will turn ON if J28 is populated or if a host is connected on the USB Type-A connector (J30).
D7 “PASS-THRU VBUS2” OFF : Green When ON, his LED indicates the presence of 5VDC on the VBUS line of the data passthrough port 2. This LED will turn ON if J31 is populated or if a host is connected on the USB Type-A connector (J33).
Figure-3-21.png
Figure 3-21: USB pass-through port VBUS LEDs

Hardware Interfaces

ICE Programming

The ICE programming interface (J19) can be used to connect an external programmer/debugger like the Atmel-ICE for accessing the programming lines of the SAMD20 and UPD301C (if using a PIM). It depends on the DBG_SEL (J20) jumper position.

Figure-3-22.png
Figure 3-22: ICE Interface and DBG_SEL jumper option

The pinout of J19 is shown in Figure 3-22 and summarized in the table below:

Connector Pin Number Pin name Description
J19 1 3V3_BRD +3.3 V target reference voltage for ICE debugger
2 ICE_SWDIO Serial Wire Debug I/O. Tied to TRGT_SWDIO through zero-ohm resistor
3 GND Ground
4 ICE_SWCLK Serial Wire Debug Clock pin. Tied to TRGT_SWCLK through zero-ohm resistor. External pull-up present
5 GND Ground
6 NC No Connection
7 NC No Connection
8 NC No Connection
9 GND Ground
10 ICE_RESET_N Target Reset from ICE debugger. Refer DBG_SEL (J20) pin out for more information

The pinout of J20 is shown in Figure 3-22 and summarized in the table below:

Connector Pin Number Pin name Description
J20 1 DBG3 Target Reset from PKoB Nano onboard debugger
2 RESET_N1_IN Global reset line used to control the SAMD20 reset line
3 ICE_RESET_N Target Reset from ICE debugger

For using the external programmer/debugger, DBG_SEL (J20) should have a jumper across pins 2-3. This would allow the external programmer/debugger to control the reset line.

SPI

The SAMD20 (U3) serves as the SPI master on the bus and communicates with UPD350s (U1 and U2) which work as SPI slaves. The SPI interface (J13) is a 2x5 header that can be used to probe the SPI traffic on the bus. The pinout for the SPI interface is shown in Figure 3-23 and summarized in the table below:

Figure-3-23.png
Figure 3-23 SPI Interface
Connector Pin Number Pin name Description
J13 1 SPI_CLK Clock line of the SPI bus between SAM20 and UPD350
2 3V3_BRD +3.3 V power supply
3 SPI_MOSI Master Out (SAMD20) Slave In (UPD350)
4 SPI_MISO Master In (SAMD20) Slave Out (UPD350)
5 SPI_SS0 SPI Chip Select line for Port 1 UPD350 (U2)
6 SPI_IRQ_N0 SPI interrupt line for Port 1 UPD350 (U2)
7 SPI_SS1 SPI Chip Select line for Port 2 UPD350 (U3)
8 SPI_IRQ_N1 SPI interrupt line for Port 2 UPD350 (U3)
9 GND Ground
10 GND Ground

I2C

The SAMD20 (U3) has a I2C Master and I2C Slave interface. The I2C Master interface is used to control the PM-PD modules. The I2C slave interface can be used to override the PSF stack configurations from an external I2C Master, usually a microprocessor or System-On-Chip (SOC).

Figure 3-24 shows the pinout of I2C interface (J14) and pull-up/pull-downs for I2C slave (J17) and I2C master (J21).

Figure-3-24.png
Figure 3-24: I2C Interface and I2C Pull-ups

The pinout of J14 is shown in Figure 3-24 and summarized in the table below:

Connector Pin Number Pin name Description
J14 1 I2C_MASTER_SCL Clock line of SAMD20 I2C Master instance
2 I2C_SLAVE_SCL Clock line of SAMD20 I2C Slave instance
3 I2C_MASTER_SDA Data line of SAMD20 I2C Master instance
4 I2C_SLAVE_SDA Data line of SAMD20 I2C Slave instance
5 GND Ground
6 I2C_SLAVE_IRQ Interrupt line of SAMD20 I2C Slave instance

The pinout of J17 is shown in Figure 3-24 and summarized in the table below:

Connector Pin Name Pin Number Pin name Description
J17 10K-Ohm 1 2 10 K-Ohm Pull-ups
I2C_SLAVE_SCL 3 4 I2C_SLAVE_SDA I2C slave signal lines
10K-Ohm 5 6 10 K-Ohm Pull-downs

By default, jumpers are populated across pins (3-5) and (4-6), which disables the I2C slave interface. For enabling the I2C slave interface, jumpers should be populated on pins (1-3) and (2-4).

The pinout of J21 is shown in Figure 3-24 and summarized in the table below:

Connector Pin Name Pin Number Pin name Description
J21 10K-Ohm 1 2 10 K-Ohm Pull-ups
I2C_MASTER_SCL 3 4 I2C_MASTER_SDA I2C slave signal lines
10K-Ohm 5 6 10 K-Ohm Pull-downs

By default, jumpers are populated across pins (3-5) and (4-6), which disables the I2C master interface. For enabling the I2C master interface, jumpers should be populated on pins (1-3) and (2-4).

UART

The UART Interface header (J16) on the EVB-PSF can be used to connect an external UART bridge to the SAMD20 and print debug messages. The pinout is illustrated in Figure 3-25 and summarized in the table below:

Figure-3-25.png
Figure 3-25: UART Interface
Connector Pin Number Pin name Description
J16 1 3V3_BRD +3.3V Power Supply
2 UART_TX UART Transmit line. Connected to TRACE_TX through zero-ohm resistor. Should be connected to the RX of the external UART bridge
3 UART_RX UART Receive line. Connected to TRACE_RX through zero-ohm resistor. Should be connected to the TX of the external UART bridge
4 GND Ground

Onboard Programmer/Debugger

EVB-PSF features the PKoB nano onboard debugger which can be used to program the SAMD20 using SWD from a host computer.

The PKoB Nano is powered by a SAMD21 which implements a composite USB device consisting of a debugger interface and a virtual COM port (CDC) as shown in Figure 3-26. The COM port interface can be used to print debug messages using the UART the SAMD20 without the need for an external UART bridge.

For more information on how to use the PKoB Nano, refer the "Programming Using the PKoB Nano" and "Using the Virtual COM port" sections.

MPLAB® X IDE can be used as a front end for programming/debugging and Data Visualizer can be used for interfacing with the CDC COM port.

For using the PKoB Nano, J20 should have a jumper across pins 1-2. This would allow the PKOB Nano to control the reset line.

Figure-3-26.png
Figure 3-26: PKOB Nano and DBG_SEL Option
SAMD20 (U3) Pin number SAMD20 (U3) Pin name PSF Pin name PKOB Nano Pin name Description
19 PA18 TRACE_TX CDC_RX UART Receive line for COM port. Connected to TX of SAMD20
20 PA19 TRACE_RX CDC_TX UART Transmit line for COM port. Connected ro RX of SAMD20
32 PA31 TRGT_SWDIO DBG0 Program/Debug Data line. Connected to Serial Wire Data line of SAM20
31 PA30 TRGT_SWCLK DBG1 Program/Debug Clock line. Connected to Serial Wire Clock line of SAMD20
N/A N/A N/A DBG2 Debug GPIO
26 RESET_N RESET_N1_IN DBG3 Target reset line. Refer ICE Programming section for more information on J20

Programming using the PKoB Nano

PKoB can be used to program the SAMD20 MCU on the EVB-PSF. It can also be used to perform common debug operations like adding breakpoints, creating real time watches, stepping into code statements. MPLAB X IDE/IPE is used as a front-end for programming. The steps for invoking the PKoB programmer/debugger on the EVB-PSF are as follows:

1

Ensure that the EVB-PSF is powered ON as shown in Figure 3-27.

2

Ensure that J20 has a jumper across pins 1-2 as shown in Figure 3-27.

3

Connect a USB Type-A to micro-B cable to the Debug USB port (J22) of the EVB-PSF as shown in Figure 3-27. The Debug LED (D2) should turn ON.

Figure-3-27.png
Figure 3-27: Using PKOB Nano for Programming Option

4

You will see a new removable drive named Curiosity appear on the host PC as shown in Figure 3-28. This drive has files with board specific information such as kit info and redirect links to the board product page.

Figure-3-28.png
Figure 3-28: Curiosity Drive

5

Launch MPLAB X IDE on the host PC and open any of the available demo projects in PSF.

6

Navigate to File > Project Properties and choose USB PD Software Framework (PSF) EVB under hardware tools menu as shown in Figure 3-29. Click on the Apply button followed by the OK button.

Figure-3-29.png
Figure 3-29: MPLAB X Project Properties

7

From the toolbar on top, click on Clean and Build icon first as shown in Figure 3-30. MPLAB X IDE should build the project using the XC32 compiler. Build Successful is displayed in the output window.

8

Now click on the Make and Program icon on the toolbar. MPLAB X would skip the build step if there were no changes detected or if you issued a clean and build before this. You will see a programming window titled PKOB nano pop up. The MCU will be erased first and then programmed. On completion, the programming window will display a Programming Complete message as shown in Figure 3-30.

Figure-3-30.png
Figure 3-30: Make and Program

Alternatively, PKoB can also be used with MPLAB X IPE to program the SAMD20 directly using a HEX file as shown in Figure 3-31. Choose the ATSAMD20E16 MCU under devices. The PKoB Nano will show up under the Tool menu if the board is connected.

Load the HEX file by using the browse button to navigate to the location. Finally, Erase the MCU and click on the Program button.

PKoB nano may enter a firmware upgrade mode the first time it is connected to MPLAB X IDE/IPE. The programming window shall display a message when it enters the firmware upgrade mode. The debug LED D2 will flash while the PKoB firmware is being updated.

Figure-3-31.png
Figure 3-31: Using PKoB Nano with MPLAB X IPE

Using the Virtual COM Port

PKoB also implements a composite USB device that includes a standard Communications Device Class (CDC) interface, which appears on the host as a Virtual COM Port. The CDC can be used to stream arbitrary data in both directions between the host and the target: characters sent from the host will appear in UART form on the CDC TX pin, and UART characters sent into the CDC RX pin will be sent back to the host.

On Windows machines, the CDC will enumerate as Curiosity Virtual COM Port and appear in the Ports section of the Device Manager as shown in Figure 3-32. The COM port number should be shown here.

On older Windows systems a USB driver is required for CDC. This driver is included in Atmel Studio and MPLAB X installations.

Figure-3-32.png
Figure 3-32: Virtual COM Port

On Linux machines, the CDC will enumerate and appear as /dev/ttyACM#.

On Mac® machines, the CDC will enumerate and appear as /dev/tty.usbmodem#. Depending on which terminal program is used, it will appear in the available list of modems as usbmodem#.

Here are the steps for using the Virtual COM port on the EVB-PSF:

1

Launch the MPLAB Data Visualizer plugin from the MPLAB X IDE toolbar. If you do not see an icon in the toolbar, then it needs to be installed from the plugin manager under Tools > Plugins Download.

2

Navigate to the MPLAB Data Visualizer window. You will see the USB PD Software Framework (PSF) EVB show up under connections tab on the top left hand side as shown in Figure 3-33. On expanding this option, you will see the COM Port number listed.

3

The COM port settings can be configured in the connections tab on the bottom left as shown in Figure 3-33. Ensure that this matches the UART settings in the firmware and click on the Apply button.

  • Baud rate: must be in the range 1200 bps to 500 Kbps. Values outside this range will be capped to these values, without warning. Baud rate can be changed on-the-fly.
  • Character format: only 8-bit characters are supported.
  • Parity: can be odd, even, or none.
  • Stop bits: one or two bits are supported.

Not all UART features are implemented in the debugger CDC. Hardware Flow control is not supported.

Figure-3-33.png
Figure 3-33: Using MPLAB Data Visualizer with PKoB virtual COM port

4

Click on the ▶ button next to USB PD Software Framework (PSF) EVB in the connections tab on top left to start streaming data through the COM port.

5

Select the COM port number of the EVB-PSF as the data source from the drop down menu on the top right Input tab as shown in Figure 3-33.

6

You should now be able to see the messages being sent over the UART under the terminal window as shown in Figure 3-33.

Debug messages need to be enabled in PSF to use the virtual COM port.

Test Access

EVB-PSF offers ample test access in the form of test points, spare pull-ups/pull-downs, grounds and signal headers. All major power supplies have their dedicated test loop with accompanying ground reference. The following sections summarizes the various test access options present on this evaluation platform.

Test Points

The following table summarizes the test point loops available on the EVB-PSF:
Reference Designator Test Point Name Description
TP2 VDD12_CORE Output of the +1.2 V internal core regulator of the SAMD20
TP3 VSW_SAM +3.3 V input power supply to the SAMD20
TP6, TP8 3V3_DB +3.3 V input power for UPD350 derived from VBUS
TP7, TP9 3V3_VSW Output of the internal power switch of UPD350
TP10 VDD18_P1 Output of the +1.8 V internal core voltage regulator of the Port 1 UPD350 (U2)
TP11 VDD18_P2 Output of the +1.8 V internal core voltage regulator of the Port 2 UPD350 (U1)
TP12 DBG_MCU_CORE Output of the +1.2 V internal core voltage regulator of the PKoB MCU
TP13 DBG_VBUS VBUS of the Debug USB micro-B port
TP14 BOOT Boot Status of the PKOB nano
TP15 VBUS1 PD Port 1 (J29) VBUS voltage
TP17 CC1_P1 CC1 line of the PD port 1
TP18 CC2_P1 CC2 line of the PD port 1
TP19 VBUS2 PD Port 2 (J32) VBUS voltage
TP21 CC1_P2 CC1 line of the PD port 2
TP22 CC2_P2 CC2 line of the PD port 2
TP23 TP_P1 FRS_EN input of the Port 1 PM-PD
TP26 TP_P2 FRS_EN input of the Port 2 PM-PD
TP28 VIN Soft Started Input Power Supply derived from DC-IN
TP29 DC_IN Main power supply input EVB-PSF
TP31 5V_BRD Output of the +5 V voltage regulator
TP36 3V3_BRD Output of the self-powered +3.3 V voltage regulator
TP37 VBUS_OR ORred VBUS of PD port 1 and 2. Input to 3V3 bus powered voltage regulator (U14)
TP38 3V3_DB Output of the +3.3 V bus powered voltage regulator
TP1, TP4, TP5, TP24, TP25, TP27, TP33, TP35, TP39, TP40 GND System Ground
TP16 GND1 Optional isolated ground for PD Port 1 (required by some DC-DC modules). Tied to GND during normal operation
TP20 GND2 Optional isolated ground for PD Port 2 (required by some DC-DC modules). Tied to GND during normal operation

Spares

The following table summarizes the spare pull-ups, pull-downs, and ground pins available for debug:

Reference Designator Header Name Description
J23 10K PUs Each of pin of this 1x5 header is tied to a 10K-ohm pull-up to 3V3_BRD supply
J24 10K PDs Each pin of this 1x5 header is tied to a 10K-ohm pull-down to ground
J25 SPARE GNDs Each pin of this 2x5 header is tied to Ground
Figure-3-34.png
Figure 3-34: Spare Pull-ups, Pull-downs and Ground

 Learn More

I. Overview of USB Power Delivery Software Framework Evaluation Kit
II. Getting Started with USB Power Delivery Software Framework Evaluation Kit
IV. Evaluating UPD301C with USB Power Delivery Software Framework Evaluation Kit

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