PID Compensator

The Proportional Integral Derivative (PID) compensator enables you to optimize the frequency response of the filter by using three (3) gain coefficients: Proportional Gain (Kp), Integral Gain (Ki), and Differential Gain (Kd). You might also choose to tune this controller by selecting the placement frequency for the single pole and two zeros, see the figure below - PID Compensator Phase and Gain Characteristics. In this figure, the (-1) slope is the equivalent to -20 dB/decade and the (+1) slope to +20 dB/decade.


The PID Compensator Transfer Function is shown below.


The PID Compensator Design window is shown in the figure below. In this window you must enter the specific information about the hardware configuration along with compensator settings, this includes:

  • PID Gains: You can define the gains for the Proportional, Integral, and Derivative gains
  • Pole / Zeros Frequency: Based on the PID Gains defined, the Digital Compensator Design Tool (DCDT) will calculate and display the frequency location of the pole (at origin) and the two zeros of the compensator.
  • Pulse Width Modulation (PWM) Switching Frequency: This is the operating frequency of the power switch (e.g., Metal–Oxide–Semiconductor Field-Effect Transistor, also known as MOSFET) and this will be defined by the microcontroller's Time Base Period Register.
  • PWM Sampling Ratio: The DCDT will use this value to calculate the sampling frequency as a function of the PWM Switching Frequency.
    • Sampling Frequency = ( PWM Switching Frequency / PWM Sampling Ratio )
    • For example, use the Trigger # Output Divider bits to configure the trigger event register and enable a specific hardware sampling frequency, see the dsPIC33/PIC24 Family Reference Manuals for more details.
  • PWM Maximum Resolution: Depending on hardware configuration settings, the PWM resolution will change. This value will be used to compute the PWM gain value, see dsPIC33/PIC24 Family Reference Manuals for more details.
  • Computational Delay: This is the time it takes for the microcontroller to execute the selected compensator mathematical algorithm. The DCDT will use the default values as defined in Table 2 of the DCDT Default Values page. It is important for you to understand that this delay will not impact the calculated digital compensator coefficients, but it will have an impact on the overall system loop gain (closed-loop) phase margin.
  • Gate Drive Delay: This is the delay associated with the hardware gate-driver + MOSFET delays, (see the section on the graphical user interface, or GUI, default values). It is important for you to understand that this delay will not have an impact on the calculated digital compensator coefficients, but it will impact the overall system loop gain (closed-loop) phase margin.
  • Control Output Min/Max: These are integer values that will be used as the absolute max/min clamping limits for the compensator output. This value clamps the value written to the target register and will have no effects on the internal compensator computations.
  • Load Defaults: This button option will load the DCDT default values for the selected compensator (see the section on GUI default values).
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