dsPIC30FXX Devices and Clock Postscaler

In some applications that make use of the clock postscaler, certain precautions need to be taken to ensure that communication with the debugger or emulator is maintained throughout a device interrogation and a programming operation.

With the dsPIC30F series of devices, such as the dsPIC30F60XX, dsPIC30F40XX, dsPIC30F30XX, and dsPIC30F20XX, that have the clock prescalers as an optional clock mode, the ICSP sequence can get out of synchronization and cause programming operations to fail. This happens because the instructions are clocked in a bit at a time and the prescaler also divides the serial data instruction stream.

What further complicates this issue is when applications also use FRC as the clock source and the target power is used. In these situations, the application code that sets up the oscillator postscaler in the OSCCON register begins executing immediately after power-up. Any subsequent MCLR or device Resets do not reset OSCCON, which causes attempts to communicate via the serial channel after this point invalid.

A workaround for this scenario in development is to run from an external crystal or oscillator source. The oscillator needs to be disabled and the target power cycled to clear the OSCCON register to program the device once more.

Additionally, a long delay can be inserted prior to the postscaler configuration setup so the debugger and programmer tool can identify the device and still leave enough time to invoke an erase operation to take place before OSCCON is modified by the application.

Alternatively, consider not using the postscaler during general code development and add the postscaler configuration only as the application development nears completion. For devices in this situation, the MPLAB PM 3 programmer can be used to dynamically switch power and may have enough current (<250 ma) to power up the target completely and keep the OSCCON register cleared.

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