Microchip FPGA Families

MIcrochip's fourth and fifth generations of FPGAs consist of three families:


Shared benefits, features, and Intellectual Property (IP)

IGLOO®2, SmartFusion®2, and PolarFireTM Field Programmable Gate Arrays (FPGAs) share several common features and benefits:

  • Instant-on operation utilizing Non-Volatile Memory (NVM). NVM technology allows these devices to be immune from Single Event Upset (SEU) configuration failures.
  • In-circuit re-programmability, allowing for efficient product development and economical field updates.
  • Proven design security.
  • Low Power, up to 50% lower operating current than SRAM FPGAs.

Math Blocks and Logic Elements

PolarFire, SmartFusion2, and IGLOO2 devices share the same logic elements and math blocks.

Logic Block

  • Fully permutable four-input Look Up Table (LUT)
  • Separate flip-flop, which can be used independent of the LUT
    • Configurable as a register or latch
    • Asynchronous and synchronous load
    • Clock enable

Math Block

  • Built-in addition, subtraction, and accumulation units.
  • Supports 18 X 18 signed, and 17 X 17 unsigned multiplication.

Consult the datasheet for the specific device you are using to find the number of logic and math blocks, as well as the available, interconnect resources between the blocks.

Libero® Design Suite - A unified Integrated Development Environment (IDE)

Libero is Microchip's easy to use Graphical User Interface (GUI) based IDE for developing all our FPGAs. Libero provides all the essential FPGA and SoC design features including:

  • Design Entry: inputting the design into the IDE.
  • Simulation: verification of function and correctness of the design.
  • Synthesis: converting the design to logic and math blocks.
  • Constraint Setting: entering the timing and power requirements for the design.
  • Place and Route: mapping synthesized design into the selected device's math and logic block and selecting the interconnects between the blocks. Libero's place and route function use the design constraints to ensure the most time-critical paths are placed and routed first.
  • Timing and Power Analysis: verifying the constraints were achieved or exceeded on the post-route design.
  • Programming: downloading the bitstream into the FPGA.
  • In-Circuit Debugging: verifying the operation on the silicon.

Royalty-Free IP for use on Microchip FPGAs

Microchip has developed an array of IP modules optimized for operation on our FPGAs using Libero. The portfolio includes bus interfaces, memories, processors, encryption, Digital Signal Processor (DSP) functions, communication processors, and other peripherals.

A complete list, including descriptions, datasheets, and download links of this rapidly growing IP family is available on the "FPGA IP Cores" page.

Size, Speed, and CPU Differences

While the IGLOO2, SmartFusion2, and PolarFire FPGAs share architectural features, they address different design needs.

Speed and Size

IGLOO2 and SmartFusion are built using a 65 nm lower power flash memory process. PolarFire is built on a much faster 28 nm Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory process. Due to the advantages of the SONOS process, PolarFire devices are larger and can run faster than either IGLOO2 or SmartFussion2 FPGAs.

Features SmartFusion2 / IGLOO2 PolarFire
Family Members 7 4
Logic Elements 6 K - 150 K 100 K - 480 K
Math Units 240 1480
Max RAM 5 Mb 33 Mb
Transcievers 1 - 5 Gbps
PCIe Gen 2 Endpoints
250 Mbps - 12.7 Gps
PCIe Gen 2 Endoints or Root Port
I/O Speeds 667 Mbps DDR3
750 Mbps LVDS
1600 Mbps DDR4
1.6 Gbps LVDS
On-Board Flash Memory upto 523 KB NVM 56KB secure NVM

Embedded CPUs

Many FPGA applications benefit from incorporating a CPU inside of the FPGA. These CPUs can either be "hard" or "soft" implementation.

  • Hard CPUs consist of circuitry added to the die. Hard CPUs do not consume any of the logic or math blocks. The maximum system clock frequency of Hard CPU is determined when the chip is designed and specified in the device datasheet.
  • Soft CPUs are synthesized designs residing on some of the device's logic and math blocks. The frequency of a soft CPU depends upon the place-and-routing of the CPU portion of the netlist and may vary from application to application.
Processor Type IGLOO2 SmarFusion2 PolarFire Note
CortexTMM1 Soft YES
CortexTMM3 Hard YES 166 MHz
RISC-V Soft YES YES YES AHB and AXI bus variants available
CoreABC Soft YES YES YES Assembly Language Only

 Learn More

For more information on Microchip's FPGA please visit the following pages:

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.